Timing-Signoff Tool Accounts For Power, Signal-Integrity Effects

For system-on-a-chip designs at 90 and 65 nm, dynamic noise greatly exacerbates the challenge of timing signoff. To accurately examine noise effects, designers need tools that provide an accurate transistor-level view of the playing field. Apache Design Solutions' PsiWinder is a critical-path and clock-tree analysis tool that considers the effects of crosstalk and dynamic power-integrity effects on timing.

Typically, timing/signal-integrity (SI) tools assume static or effective supply rails and provide only linear approximations. Consideration of combined power and SI effects requires a transient simulation of instance-based dynamic V_DD/V_SS waveforms along with crosstalk noise. A static analysis environment too often won't muster the accuracy to pull this off. PsiWinder addresses this by providing a Spice-accurate, time-point-by-time-point simulation of waveforms.

PsiWinder considers crosstalk noise, including aggressor/victim identification, sensitization, and window alignment. It also analyzes dynamic voltage-drop and ground-bounce effects using instance-specific V_DD/V_SS waveforms generated by Apache's RedHawk power-integrity analysis tool, which is tightly integrated with PsiWinder (see the figure).

The tool supports process corner conditions for each device, alignment and transition of each coupling signal, and the minimum and maximum dynamic voltage drop of each cell for a thorough verification of on-chip variation.

Through use of a Spice engine and advanced nanometer device models, PsiWinder performs precise calculations of actual signal slopes and loading. This eliminates the pessimism built into standard device libraries.

PsiWinder will be available in the third quarter with annual licenses starting at $150,000. Each license includes 10 integrated Nspice engines for distributed simulation of multiple critical paths.