David Maliniak’s DesignCon Blog: Day 2

Feb. 8, 2006
It’s amazing what the opening of exhibitions can do for the attendance at an industry event. Whereas yesterday DesignCon was deadly quiet, today was quite a different story. A good crowd of attendees flowed in and out of the technical sessions and onto th

It’s amazing what the opening of exhibitions can do for the attendance at an industry event. Whereas yesterday DesignCon was deadly quiet, today was quite a different story. A good crowd of attendees flowed in and out of the technical sessions and onto the small exhibition floor. But at least Silicon Valley’s engineering force turned out for the event, with a keynote address by National Semiconductor’s Brian Halla being a key draw.

I began the day taking in the start of a management forum panel titled, “Why is EDA Stagnating, Or Is It?” It was a session that promised fireworks, but the portion I caught didn’t deliver. Jim Hogan, a former EDA executive (Cadence) turned venture capitalist turned private investor, opined that EDA is sliding down the inevitable slope toward commoditization. As this occurs, there’s less and less differentiation between vendors’ offerings. As a result, says Hogan, growth in EDA will occur outside the core. Hogan pointed to electronic system-level (ESL) tools and design-for-manufacturing (DFM) methodologies as the best opportunities for growth.

Most of the other panelists agreed with Hogan, more or less, with Gartner Dataquest’s Chief Analyst Gary Smith the lone dissenter. “I’m an optimist for EDA,” says Smith, “but yes, we’re stagnating.” Smith sees a noticeable rise in the use of in-house development tools, particularly in ESL, owing to the scant availability of toolsets. Yet, says Smith (as he has for a good many years now), ESL will ultimately spur growth in EDA. ESL has been slow to see adoption thanks, at least in part, to the dearth of evangelists singing its praises. Smith also pointed to the stubbornness among semiconductor vendors to see themselves as being in the “systems business” as opposed to the “component business.”

I spent some time with Kaushik Sheth, founder and CEO of startup Rio Design Automation. Rio is in the IC/package co-design business and has signed up at least four significant customers. According to Sheth, all users of the company’s RioMagic tool report outstanding results owing to the tool’s concurrent approach to silicon and package design. Previously, ICs and their packages were largely designed in sequential fashion, with package design being held up until the chip’s I/O pad ring was frozen. RioMagic sits between the chip and package design tools and uses the industry-standard OpenAccess database to facilitate a concurrent flow. As a result, package design exploration can begin in the early planning stages of the IC flow. You end up with a package design with few or no iterations as well as an optimized die to put in it.

An enjoyable lunch in the company of Lauro Rizzatti, general manager of EVE USA, yielded the news that EVE is doing well and gaining traction in numerous markets. Stay tuned for more news from this vendor of hardware-assisted verification platforms in the coming weeks and months. They’re one of the few vendors in their market who’ve made much noise at all recently.

I received an update from Canadian IP vendor MOSAID, who acquired Virtual Silicon in October of last year and have been busy since integrating the companies’ offerings. In particular, Graham Allan, MOSAID’s director of marketing for its IP division, stressed the synergies between its digital frequency synthesizer and DDR SDRAM memory controller. The frequency synthesizer, which boasts an output range of 44 MHz to 3000 MHz, has the low-jitter output that the memory controller needs for stability. Both of these functional blocks can be teamed with MOSAID’s Mobilize power-management IP to form a mobile DDR controller and memory interface subsystem.

In chatting with Vess Johnson and Dennis George of Nascentric, I learned that at least two patents are forthcoming for technology that’s at the heart of Nascentric’s Nascim fast-Spice simulator. Nascim relies on current-based modeling for both devices and parasitics (interconnects), a technique that enables the tool to handle much larger designs than previous generations of fast-Spice simulation. Nascentric has 10 more technology patent applications outstanding.

Apparently, rumors have been circulating of the imminent demise of Sequence Design. These rumors never made it to me at my home base in New Jersey, but CEO Vic Kulkarni and his newly recruited marketing director, Holly Stump, wanted to put them to rest anyway. Sequence now sports a handsome number of customers in the wireless and handheld markets as well as in consumer electronics. This week, they’ve announced that Genesis Microchip has chosen Sequence’s CoolTime for voltage-drop analysis and power-grid integrity. Genesis has already successfully taped out a next-generation design using Sequence’s flow.

In other recent news, Sequence has partnered with DongbuAnam, the large Korean pure-play foundry, to develop a power-aware reference flow for process technologies at 130 nm and below. The flow will incorporate Sequence’s full array of tools, including PowerTheatre for SoC power analysis and optimization; CoolPower for physical power optimization for standby leakage as well as dynamic power; and CoolTime, for static and dynamic power-grid analysis and optimization.

Look for a final installment from DesignCon tomorrow. Until then…

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