System Analyzes Chip Performance At Earliest Design Stage

ChipEstimate has upgraded its flagship InCyte early chip-planning system to enable performance analysis at the earliest phase of the chip design cycle. The system now offers designers quantifiable feedback regarding the feasibility of achieving various performance targets for their chip. The new analysis capability is technology-node-specific, process-specific, and IP-specific. It allows designers to make better decisions regarding chip architecture tradeoffs to minimize the risk of missing performance goals. It also lets them push the limits of technology with greater success.

The company added other significant features to InCyte. For instance, the interconnectivity of IP and other design components within a chip can now be incorporated into design specifications, enabling more accurate chip planning and estimation. Also, design teams can now communicate their architectural specifications visually into InCyte with an easy-to-use tool like Microsoft Visio. Users simply drag and drop IP and other design components into block diagrams that InCyte uses to estimate the size, power, and cost of the resulting chip. Another enhancement links design specification data directly into leading EDA implementation flows from Cadence, Magma, Mentor Graphics, Synopsys, and other vendors. Finally, the system helps guide user selection of IP libraries and provides quantified feedback on the particular density, power, leakage, and performance of a given library.