Tool Closes Verification Loop Between ESL And Implementation

June 2, 2008

Verifying and validating the behavior of a hardware component requires appropriate sequences of stimuli (test cases) and comparison of the results provided by the device under test with the reference results. This verification is often done at the register-transfer level (RTL) and requires up to 70% of the implementation time. A major difficulty consists in describing and applying test cases that are representative of the use of the device in real conditions.

With CoFluent Studio, hardware components and their use cases are specified using graphics and ANSI C/C++ code. Transaction-level SystemC code is automatically generated from these descriptions. The organization (functional pipeline) and performance of components can be analyzed and optimized early in the context of realistic conditions of use by executing abstract models. This removes the need for intricate and effort-prone cycle-accurate and bit-accurate models. These reference transaction-level and use case models constitute executable specifications that guide the hardware implementation.

Combined with a high-level synthesis tool, a full C-based ESL to implementation flow can be achieved. C/C++ algorithms are progressively integrated and refined until functional bit-accurate fixed-point simulation is obtained with CoFluent Studio. They are then translated into synthesizable RTL using a high-level synthesis tool.

Simulation of generated RTL blocks in a dedicated environment delivers precise calibration information that is used for back-annotating the ESL simulation in CoFluent Studio. This validates the reference transaction-level and use case models.

The ESL use cases can validate the cycle-accurate implementation in two ways:

The SystemC code automatically generated by CoFluent Studio can be used as testbench for driving the simulation of a cycle-accurate model of the component, provided that a SystemC adaptation layer is written for protocols conversion.
Language-neutral time-accurate test pattern files can be generated from the reference transaction-level model. These files are used to validate the time-accurate behavior of the detailed hardware component model in a dedicated testbench. The test pattern files that are generated are free and purely textual, providing compatibility to any simulation tools.

CoFluent Studio helps hardware designers close the validation loop between ESL executable specifications and use cases, and cycle-accurate implementation and testbench.

Contact CoFluent Design directly for pricing and delivery information.

CoFluent Design
www.cofluentdesign.com

About the Author

David Maliniak | MWRF Executive Editor

In his long career in the B2B electronics-industry media, David Maliniak has held editorial roles as both generalist and specialist. As Components Editor and, later, as Editor in Chief of EE Product News, David gained breadth of experience in covering the industry at large. In serving as EDA/Test and Measurement Technology Editor at Electronic Design, he developed deep insight into those complex areas of technology. Most recently, David worked in technical marketing communications at Teledyne LeCroy. David earned a B.A. in journalism at New York University.