Verification Suite Enables Reuse Of VHDL/Verilog Testbenches

Aug. 1, 1998

One of the largest bottlenecks in electronic design is the functional verification of complex ASICs and system-on-chip (SOC) designs. The QuickBench verification suite is said to enable nearly complete reuse of the complex VHDL or Verilog testbenches that engineers must develop to thoroughly verify their designs. The ability to easily and accurately reuse earlier work in the verification process will greatly assist in reducing overall time-to-market.For verification reuse to be practical, the information used to construct testbenches must be modular, easily understood and easily assembled into new testbenches. The QuickBench suite enables the design of testbenches using task-appropriate levels of abstraction, which define modular, reusable and well documented verification components.The suite consists of three modular products that are available separately or as a package. Two of the new products, QuickBench Manager and QuickBench Sequencer, join QuickBench Modeler, an enhanced version of the current QuickBench 2.1. QuickBench Manager manages testbench data and testbench generation flow. Quickbench Modeler automates the design and generation of the structural and timing specifications of testbenches, and QuickBench Sequencer automates the design and generation of verification stimuli. The suite runs on HP, Sun and Windows 95/NT platforms.


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