System Provides High-End Synthesis

Nov. 1, 1998

The integration of firm's ispDS+ Logic Fitter v5.2 for high-density ISP device design and Synplicity's Synplify VHDL and Verilog-HDL synthesis offerings has resulted in the new ispHDL System for Synplicity for high-density ISP device design. The program is designed to provide maximum value and performance for any logic design and complements firm's full lone of power ispHDL tools linking VHDL, Verilog-HDL and in-system programmable (ISP) logic devices to improve time-to-market. The new package is supported on a PC platform and the base system version supports firm's ispLSI 1000E, 2000, 2000V, and 3000 device families.

Comments

To join the conversation, and become an exclusive member of Electronic Design, create an account today!