CPLD Is Laden With Registers and Macrocells

With 1152 registers and 840 general-purpose macrocells, the ispLSI 8840 complex programmable logic device (CPLD) is being called the world's largest in-system-programmable logic device. The 38,000-gate CPLD sequesters its macrocells in seven Big Fast Megablocks (BFMs), each consisting of six 20-macrocell-wide Generic Logic Blocks (GLBs) with 44 inputs per GLB.The device offers both high-speed global and BFM interconnect using a Global Routing Plane (GRP) architecture. Acting as a silicon backplane, the GRP delivers 2-ns global interconnects. A second-generation product-term sharing array supports up to 28 product terms per macrocell output. Pin-to-pin logic delay is specified as 8.5 ns with internal operating frequency of 100 MHz. A broad library of design tools is ready to go.