Co-Verification Tool Supports PowerPC Cores

Sept. 1, 1998

Embedded system designers using IBM PowerPC cores, as well as system-on-chip designers, can take advantage of the full power and feature set of Virtual-CPU for hardware/software co-verification tool. V-CPU provides embedded designers with a virtual environment for debugging their software and hardware and allows them to use the IBM core master and slave bus models with the IBM PVS instruction set simulator and software debug tools integrated with their favorite HDL logic simulator. Under the agreement, the firm has licensed IBM's core-based Verilog and VHDL bus models and its PVS, both of which will be packaged and distributed with V-CPU. PVS is an instruction-level simulator for the PowerPC architecture with an integrated high-function GUI. The PVS simulator presents a software view of the PowerPC architecture and models the PowerPC instruction set, register space and memory space.


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