Architecture Optimizes High-Capacity Chip Design

March 1, 2001

The Hierarchical First Encounter (HFE) design system is offered as a complete solution for the chip-level implementation of multi-million gate, high-performance system-on-chip (SoC) designs implemented using deep sub-micron technology. The HFE design system uses a technology that delivers the capacity of block-based design tools while maintaining the ability to optimize traditional flat methodologies. The software complements popular design environments, such as software tools from Avant!, Cadence and Synopsys. Other features of the new software include: a partition optimizer; hierarchical interconnect synthesis that produces the final top-level interconnect between the hierarchical blocks; top-level router for high-performance routing of the top-level signals between the blocks; top level optimization that includes cell re-sizing, buffer insertion, and load splitting; and clock tree routing, which provides a balanced clock tree. HFE requires use of the company's First Encounter software that provides the physical engines. Price for a twelve-month license starts at $105,000. HFE is also available with First Encounter and its options in a package called SoC First Encounter. A twelve-month license for the package starts at $245,000.


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