To Shake Its Malaise, EDA Must Look To Where Design Is Really Happening

Jan. 7, 2010
EDA is missing the boat, says Paul McLellan. Market fragmentation is driving down ASIC volumes and differentiation is done in software, not hardware. To right itself, EDA must look toward generic silicon fabrics and higher abstraction levels.

EDA is in trouble. It has become a fat change-averse business in a fast-changing environment. Even as the electronic system market is growing strongly, it is fragmenting. More and more of the volume is in comparatively small markets (see the figure). No one market is as dominant as, for example, the PC was in the 1990s.

The reasons lie in the economics of semiconductor manufacturing. A chip now costs so much to design and produce that only the largest markets can justify the cost. Smaller ones must aggregate demand so multiple systems can be designed around a single chip. Differentiation is accomplished in programming either at the hardware level (FPGA and programmable system-on-a-chip, or PSoC) or the software level. Meanwhile, EDA remains focused on hardware design.


In the future, the dominant design paradigm will start with software, probably written in C/C++. Some of that software will be synthesized onto FPGAs as hardware. The rest will be compiled to run on processors implemented in the FPGA. But it’s more than just the software necessary to run on the FPGA or SoC.

It’s also about signing off hardware that co-optimizes the software. The idea is that we need to get the software that specifies the system right on a conceptual level, and then hardware design becomes a matter of creating a silicon fabric (SoC, PSoC, or FPGA) that can run the software fast enough at minimal power. There are two key pieces of technology.

The first is high-level synthesis, which should be seen as a type of compilation of behavior into hardware. In the end, the system product delivers a behavior or application. It isn’t simply some sort of productivity tool as register transfer level (RTL) designers move up to the next level. RTL designers will be bypassed, not made more productive.

The other key technology is FPGA and PSoC technology itself. Today, FPGAs offer almost unlimited capacity and unlimited pins. For some applications, especially ones requiring some analog, PSoCs provide less flexibility but can hit a sweeter spot in the power/performance/price matrix. FPGAs will become the default implementation medium.


The classic argument for avoiding FPGAs was that you could reduce the manufacturing cost enough to amortize the design cost of a chip. But very few designs run in high enough volume to amortize the cost of doing an SoC or ASIC in today’s leading-edge processes, and the cost and risk are rising fast. FPGAs remove a lot of the silicon risk.

FPGAs represent more than half the volume of leading-edge process nodes at the big foundries. They are the first logic in a new foundry process, and they drive the semiconductor learning curve. Also, FPGAs drive up the yield because their structural regularity is much like a memory but in a standard CMOS logic process. So if you need to do a 45- or a 32-nm design, the easiest approach is to go with FPGAs. Only the highest-volume consumer markets can justify a custom SoC.

However, these high-end FPGAs require an ASIC-like design methodology, not just tools from the FPGA vendor. The challenge for EDA in this new world is to address these system-scale designs implemented in FPGAs. That is largely not in the big semiconductor companies, i.e., the 20% of EDA’s customers that bring 80% of their revenue. It is much more dispersed.

This resembles the democratization of design by ASICs in the early 1980s. Then, front-end IC design was pushed out into the system companies because that’s where the differentiation was. Now, the differentiation has moved up to software. System companies no longer care about IC design, and it has almost completely moved back into the semiconductor companies.

But apart from a few startups, EDA is largely ignoring this new world where the most important layers are higher than they used to be, software and quasi-software that can be mapped into or onto hardware. Of course it is a “innovator’s dilemma,” because the big semiconductor companies that are EDA’s main revenue source are the few remaining places where chips are designed from the ground up. But most electronic systems designs are going on in electronic system companies.

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