Memory Verification IP Offering Supports Third-Party Simulators

April 7, 2011
The Cadence VIP Catalog provides everything required for block-level verification of standards-based design IP with extensive protocol checks, tests, and coverage reports.

The Cadence VIP Catalog contains a broad spectrum of verification IP, enough to cover the verification of full-chip SoC designs with the myriad of standard-based protocols and interfaces likely to be found there.

Today’s typical system-on-a-chip (SoC) designs comprise a large number of standard protocols and memories. Standard or not, these intellectual property (IP) blocks require verification, and doing the job from scratch takes lots of time, effort, and expertise.

Verification IP (VIP), as opposed to design IP, aids in this effort by automating the verification process. It checks for protocol compliance with reference to the specification, verifies host and device designs, and includes multiple state-machine monitors for both sides of the interface. It also generates and drives test sequences to fully shake out the design IP.

In the wake of its acquisition of Denali, Cadence has rolled out the Cadence VIP Catalog combined VIP offering. From the Denali stable, Cadence has harvested support for golden memory models. Denali’s VIP supported protocols such as PCI Express and SATA, while Cadence’s collection included AMBA and MIPI, among a broad range of more than 30 protocols.

The Cadence VIP Catalog fits under the umbrella of the company’s larger EDA360 vision, which goes beyond traditional EDA tool flows that concentrate on the design of physical silicon to a broader system-level focus. The VIP offering brings capabilities that extend into that system-level realm.

In the context of traditional flows, the Cadence VIP Catalog provides everything required for block-level verification of standards-based design IP with extensive protocol checks, tests, and coverage reports. It delivers support for numerous new protocols such as AMBA4, MIPI M-PHY, MIPI DigiRF, MIPI UniPro, and others. The catalog also is universally compatible with the Unified Verification Methodology.

For full-chip SoC-level verification, the catalog offers a broad range of protocols with a consistent testbench interface. It is suited for designers who don’t necessarily want to dig deeply into each of the many protocols that may reside on a given SoC, but are more interested in how they interact with each other. For these design teams, the availability of verification metrics and a scoreboard is critical. They are looking to verify interconnects, control lines, and dataflow.

The catalog addresses a further level of abstraction at system level with an eye toward hardware/software co-verification. In this realm, design teams call on high-performance hardware-assisted verification. Here, the verification environment is much larger with simulation of whole systems.

Users are looking for a software-centric view, wanting to see from a software perspective what the system does when driving stimulus. Further, in such scenarios, a robust environment for verification reuse is paramount. The Cadence VIP Catalog supports these applications with accelerated VIP that reuses the register transfer level (RTL) testbench.

Rather than using large regression farms to perform this sort of system-level verification, most design teams prefer to move into an accelerated Palladium XP-based environment, which can take verification of standard protocols to near-emulation speeds. It also affords the ability to stimulate the verification run from the software environment, which moves the verification up to the transaction level and the virtual register-interface level.

Cadence Design Systems

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