IMEC, the Belgium-based nanotechnology research center, announced at this week's VLSI Symposium that it has improved the performance of its planar CMOS using hafnium-based, high-k dielectrics and tantalum-based metal gates for the 32-nm CMOS node. The inverter delay fell from 15 ps to 10 ps. IMEC also simplified its high-k/metal-gate process by eliminating six of the 15 process steps.
The performance improvement was achieved by applying a thin dielectric cap between the gate dielectric and metal gate. Both gate-first and gate-last integration schemes were successful. The gate-last scheme is currently in production for high-performance products. The gate-first option is attractive for low-cost applications, but only if its complexity can be reduced to the standard CMOS process flow. One possible solution is the use of a dual-metal, dual-dielectric process flow using mostly hard masks to selectively pattern nMOS and pMOS regions.
IMEC increased the respective performance of nMOS and pMOS transistors by 16% and 11% by applying conventional stress boosters. This is the first time IMEC has demonstrated the compatibility of conventional stress memorization techniques and a high-k/metal gate process.
The research center has also simplified process complexity from dual-metal, dual-dielectric to single-metal, dual-dielectric by using soft-mask processes and wet removal chemistry. This change eliminates six process steps. It also allows simpler gate-etch profile control and offers better prospects for scaling. In addition, IMEC proved that the use of La and Dy capping layers do not introduce reliability issues.
Research results were obtained in collaboration with IMEC’s sub 32-nm CMOS partners, including Intel, Micron, Panasonic, Qimonda, Samsung, TSMC, NXP, Elpida, Hynix, Powerchip, Infineon, TI, and ST Microelectronics.