USB Connectivity Added To eSi-RISC Processors

Wokingham, UK and Bielsko-Biala, Poland: EnSilica and Evatronix teamed up to create a fully featured eSi-RISC processor SoC incorporating USB 1.1, 2.0, and 3.0 connectivity. EnSilica integrated Evatronix’s USB 1.1, 2.0, and 3.0 IP solutions, including support for USB OTG, into its eSi-SoC Generator tool. The tool automatically produces processor subsystem RTL, including bus arbitration, enabling USB SoC-based solutions to be rapidly generated.

Depending on customers’ system-level requirements, support is provided for low-speed, full-speed, high-speed and “SuperSpeed” devices. The new SuperSpeed standard supports data rates up to 5Gb/s.

Evatronix’s configurable IP allows hardware resources to be optimised to the end application’s performance requirements. These include parameters like the number of endpoints and options dedicated for USB direct-memory-access (DMA) engine support. Suspend and resume power-management functions are supported, reducing the overall system power.

All of the USB software stack’s features, including a “Mass Storage Class” option, make it possible to deploy a low-cost USB processor subsystem, reducing risk, cost, and time-to-market. The company’s range of USB IP is fully certified by the USB-IF.

In addition, there’s a set of eSi-Connect peripherals that include cache and static memory interfaces through to peripherals such as I2C, UART, SPI, a Smartcard (ISO7816-3) interface, Ethernet, RTC, system timers, DMA, and encryption accelerators.

The eSi-SoC Generator supports either single- or multi-processor architectures with a mixture of AMBA APB-, AHB-, or AXI-based buses. The SoC architecture and eSi-RISC processor configuration is described by an XML format file.

Each eSi-RISC processor can be configured separately within the XML file, with over 50 configuration options available for each processor. These include the base 16- or 32-bit data word support, memory architecture, addressing modes, and extension instructions (load multiple, bit field extraction, single-cycle multiply, and multi-cycle divide). As a result, each processor is able to be optimised for the end application, reducing silicon resources and minimising the overall system power.

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