VTI Bonds ASICs To MEMS Wafers

VTI Technologies is pioneering a way to package Microelectromechanical systems (MEMS) and ASICs on the same wafer in hopes of creating smaller sensing devices for large-volume production. In current processes, MEMS wafers are created first and then joined to ASICs. VTI's process, dubbed Chip-on-MEMS (CoM), bonds ASICs to MEMS wafers before dicing. To achieve this, ASIC chips are "flip-chipped" onto the MEMS wafer, which has already had solder points and redistribution and isolation layers applied to it. After the ASICs are added, both sets of chips are isolated using a passivation layer. VTI was able to engineer a model that has a footprint of 4 square millimeters and a height of less than 1 mm. At this level, even final testing and calibration are wafer-scale processes. The result: thinner chips that will scale MEMS devices to one-third their current size, according to VTI. The company's next move is to develop manufacturing processes that will allow for volume production of more complex sensing components that use the Chip-on-MEMS technology. Multiple ASICs stacked on MEMS devices will pave the way to small sensing devices for use in high-volume, low-cost applications. "This Chip-on-MEMS is a radical step away from conventional packaging as it is simply an extension of wafer-fab processes," Heikki Kuisma, Vice President of Research at VTI, said in a statement. "This \[research\] is an important step in bringing down the cost and size of sensing technology for volume production."