3.3V PLD Family’s Macrocell Count Is Boosted To 192

July 1, 1999

Four new devices have been added to the rapidly expanding 3.3V SuperFAST High Density PLD family: the ispLSI 2192VE, offering 192 macrocells with 5-ns/180-MHz (Tpd/Fmax) performance; the 96-macrocell ispLSI 2096VE and 64-macrocell ispLSI 2064VE, boasting of 4.5-ns/200-MHz operation; and the ispLSI 2128VE, delivering 128 I/Os, 128 macrocells and 5-ns/180-MHz performance. The ispLSI 2000VE family is said to offer the fastest registered I/O timings of any 3.3V CPLDs at these density levels, with input-to-clock setup times (Tsu) to 2.5 ns and clock-to-output delays (Tco) to 3.0 ns. The devices also provide 5V-tolerant I/O pins. Programming times for SuperFAST devices have been reduced by >80%, with ispLSI 2000VE devices’ times pegged at less than two seconds.

About the Author

Staff

Articles, galleries, and recent work by members of Electronic Design's editorial staff.

Sponsored Recommendations

Comments

To join the conversation, and become an exclusive member of Electronic Design, create an account today!