Electronic Design

A 45<sup>th</sup> DAC Post-Mortem

Last week’s 45th Design Automation Conference (DAC) in Anaheim was my twelfth consecutive DAC, and it was surely the most interesting and different I’ve experienced in journalistic terms. Yeah, that was me traipsing around the show floor with my colleague Damian Mendez in tow, toting a great big video camera. It was my first experience in documenting DAC in video, and I would term it a success (watch the video).

As for DAC itself, it seemed to be a somewhat lightly attended show but few exhibitors were complaining. Many boasted of full demo suites that had been booked up well in advance of the exhibition’s opening bell. As usual, the Program Committee put together a varied and highly interesting technical conference that had something for everyone concerned with some aspect of EDA, from highly abstract ESL methodologies to the nitty-gritty of mask preparation.

I came away from DAC this year with more of a sense of optimism than I have in recent years regarding the EDA industry’s outlook. I’m not quite sure why that should be, though. I saw, nor heard about, no breakthrough technologies that are guaranteed to smash the well-known verification bottleneck. I didn’t learn of any technologies that will alleviate concerns about silicon yields at 45 nm and below. Yet, there were fewer mopey faces amongst the many technologists and marketers I interacted with than I recall last year.

Rather than stunning breakthroughs, my 45th DAC was marked by hearing about a good many incremental improvements in various areas of the design flow. For example, Mentor Graphics came to DAC with its spiffed-up edition of the place-and-route system it acquired with Sierra Design Automation, now dubbed Olympus-SoC. For its part, Synopsys came with its Zroute routing engine for IC Compiler. Each company is betting that their new technology will make for inherently better silicon at 45 nm.

Some influential industry observers, notably Gary Smith (of his eponymous EDA research and analysis firm) believes that this is the year of analog design. It could well be, based on what I saw. CLK DA’s Amber family of transistor-level statistical static-timing analysis tools were impressive, as was Extreme Design Automation’s Goldtime MXO, a timing analysis tool aimed at multi-mode, multi-corner timing optimization and signoff.

Also in the analog realm was Magma’s Titan chip-finishing suite, which marks Magma’s thrust into mixed-signal design automation. Agilent EEsof EDA showed its wireless design library for its Advanced Design System (ADS), a 3D planar electromagnetic simulator. Meanwhile, Ansoft has added statistical eye-diagram analysis of serial links to its popular Nexxim simulator.

There was plenty happening on the verification front as well. Momentum seems to be building behind the new TLM 2.0 standard out of the Open SystemC Initiative, with support coming from numerous quarters. I saw an interesting demo of OneSpin’s SystemVerilog Assertions (SVA) library, which gives users of the company’s 360 Module Verifier the ability to capture timing diagrams as SVA assertions.

A highlight of the week for me was the opportunity to moderate a DAC Pavilion panel on recommended design rules. If you were in the audience on Wednesday afternoon, I hope you enjoyed the discussion as much as I did. I’d like to take this opportunity to thank Norma Rodriguez of AMD, Michael Buehler-Garcia of Mentor Graphics, and Walter Ng of Chartered Semiconductor Manufacturing for their highly insightful participation. I’d also like to thank Dave Reed and Cedric Iwashina of Blaze DFM for inviting me to moderate.

Well, the best way to review my week at the 45th DAC is to simply visit our DAC page on the Electronic Design Web site, where you can see and hear it pretty much the same way I did. I hope to see you all next year in San Francisco!

Electronic Design DAC videos
http://electronicdesign.com/shows/DAC

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