Using a 64-bit RISC design that simplifies instruction sets to accelerate performance, the VR12000-300 microprocessor is compatible with the MIPS IV instruction set architecture. The super-scalar µP contains multiple pipelines that allow it to execute several instructions per clock cycle. It can re-order these instructions to make efficient use of its execution units, resulting in estimated top-end performance ratings of 16.8 SPECint95 and 27.8 SPECfp95. Its improved micro-architecture maintains binary and pin-level compatibility with the VR10000-series of µPs. Applications are found in supercomputers for weather forecasting and geophysics calculations, top-end UNIX workstations and servers, multimedia applications and Internet servers.