The initial 8-bit RISC MCUs using the firm’s PIC18CXXX architecture are OTP MCUs intended to deliver system-on-a-chip (SOC) and system partitioning capabilities in embedded applications. The PIC18CXXX architecture is an enhanced RISC core that’s upward-compatible from the firm’s mid-range and high-end cores, providing a seamless migration path. The PIC18CXXX architecture offers up to 2 Mbytes of program memory, a C compiler-friendly development environment, and up to 10 MIPS performance at 40 MHz.The PIC18C242 and -442 feature 8192 x 16 bits of OTP program memory and 512 bytes of user RAM. The PIC18C252 and-452 provide 16,384 x 16 bits of OTP program memory and 1536 bytes of user RAM. An in-circuit emulator and a C compiler are also available.