Bringing manufacturing awareness into the design loop is the only true form of what has been termed "design for manufacturing," or DFM. Synopsys's latest thrusts into the DFM arena declare the EDA giant's intention to bring statistical analysis to bear on the problems that are posed by design-induced process variation.
By enhancing the Star-RCXT parasitic-extraction and PrimeTime static timing-analysis tools, Synopsys enables its customers to better control timing margins and produce more robust designs. From a single extraction run, the updated Star-RCXT VX delivers both corner-and variation-based parasitic information, which is then fed into PrimeTime for timing analysis (see the figure, a).
PrimeTime, now updated as Prime-Time VX, analyzes device as well as interconnect variations using statistical techniques. It also performs concurrent within-die and die-to-die modeling. The tool delivers 5% path accuracy when compared with HSpice Monte Carlo analysis (see the figure, b).
PrimeTime VX lets designers sidestep one of the pitfalls of traditional cornerbased analysis, which is increased guardbanding and large timing margins. It also avoids the need to apply large margins and the potential risk of over-or underdesign. The results from both Star-RCXT VX and PrimeTime VX are fed into IC Compiler for implementation.
A new tool, PrimeYield, helps accelerate time to yield by looking forward into the manufacturing loop and fixing problems prior to tapeout. The tool takes in foundry data and a placed-and-routed design from IC Compiler and gives users three ways of examining potential yield problems: lithography compliance checking, model-based CMP checks, and critical area analysis.
PrimeYield is available now for $225,000. Contact Synopsys for pricing and availability information for Star-RCXT VX and PrimeTime VX.