Pure-play silicon foundries are joining hands with EDA vendors to offer libraries that are verified in silicon and validated on tools. In this way, foundries can ease their customers' path into system-on-a-chip (SoC) design at geometries of 150 mm and smaller.
To that end, Taiwan Semiconductor Manufacturing Co. (TSMC) has teamed with two dominant tool suppliers to accelerate nanometer design cycles. Cadence Design Systems is to be the first full-line distributor of TSMC's standard-cell, I/O, and memory libraries.
Cadence hopes to support an all-encompassing design paradigm that requires tight links across the design chain. "Not only are the libraries validated with Cadence's Encounter platform, but they're also proven in silicon on TSMC's processes," said Charlie Huang, Cadence's VP of marketing.
"Modeling issues at these geometries will not be totally understood just on the design-rule and Spice-model levels," Huang continued. "Problems with the models will only surface once real designs are implemented with real libraries and tools. We're taking steps to obviate these issues."
Cadence is now offering standard-cell and I/O libraries for 150-, 130-, and Nexsys 90-nm TSMC processes. Memories for TSMC's 130-nm process will be added in the second quarter of 2003; 90-nm memories will follow in the fourth quarter.
TSMC is covering its bases by working with Synopsys, which has also validated the Nexsys 90-nm libraries for its RTL-to-GDSII tool flow. The libraries support all Synopsys views used in the design flow, including .lib (with noise-modeling capabilities), .db, .plib, .pdb, Apollo, Astro, and the Milkyway design database.
Cadence Design Systems