Electronic Design

ARM, Synopsys Partner For SystemVerilog Verification

A reference methodology to define a coverage-driven verification architecture using SystemVerilog is in the works from ARM and Synopsys. The companies will publish the methodology in the co-authored SystemVerilog Verification Methodology Manual (VMM), providing architecture guidelines and best practices for more effective and faster verification of complex systems-on-a-chip (SoCs). The VMM is scheduled to be available at June's Design Automation Conference.

"As the industry reacts to complexity with collections of point tools to address verification, new problems have arisen," says Swami Venkat, director of marketing at Synopsys. These problems manifest themselves in fragmented, disjointed verification methodologies. System and RTL verification flows are unnecessarily duplicated, assertion methodologies are separated into dynamic and formal flows, and there is a nonstandard verification IP infrastructure.

In the SystemVerilog VMM, ARM and Synopsys will bring their strengths to bear in crafting a unified, comprehensive methodology that addresses all aspects of functional verification (see the figure). This will include design-for-verification techniques using SystemVerilog assertions for formal analysis and dynamic verification. It also will cover use of constrained-random stimulus generation techniques and of coverage metrics to quickly close verification. And, providers of verification IP will have a consistent, well documented architecture to work from for more easily integrated verification IP.

The VMM itself comprises a "how-to" book that takes its inspiration from the successful Reuse Methodology Manual developed by Synopsys and Mentor Graphics. Among the VMM's authors will be Verification Guild moderator Janick Bergeron; Synopsys scientists Phil Moorby (Verilog's creator) and Peter Flake; and ARM's worldwide director of design methodology John Goodenough and director of SoC verification Andrew Nightingale.

Included within the VMM will be a blueprint for the overall verification architecture as well as specifications and examples of testbench building blocks and assertion libraries. No publisher has been named yet.



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