Development of an automated analog/mixed-signal (A/MS) design flow has been the focus of much attention over the past few years. Primarily, this focus has centered on five main areas: A/MS standard languages, logical synthesis, analog and digital co-simulation capabilities, analog and digital block integration, and physical synthesis. While there's no disputing that great strides have been made in each of these areas, more development is needed before the industry can claim victory at the hands of a fully automated, easy-to-use A/MS design flow.
Perhaps the most impressive stumbling block of all is logical synthesis. Its absence forces designers to manually translate a design's behavioral description into a transistor-level or implementation-level representation. That process requires expert knowledge of analog design nuances, transistor-level descriptions, and the emerging A/MS extensions to the current Hardware Description Language (HDL) standards. It's time consuming and tedious work. Plus, it can be error-prone.
Finding a suitable analog synthesis solution will significantly help proliferate the use of an automated A/MS design flow by rallying the community of designers around a set of tools and a methodology that it can actually trust. This is a critical point, because as Mar Hershenson, founder and CEO of Barcelona Design, points out, "Analog synthesis is such a Holy Grail for A/MS design that prior attempts have served only to muddy the definition and feed the cynicism."
A synthesis method is required for analog circuit design that can provide real and substantial improvement over previous methods. According to Hershenson, "A tool of this nature will break the analog logjam and enable the system-on-a-chip (SoC), post-PC revolution to begin."
True analog synthesis isn't the only stumbling block facing the development of an automated A/MS design flow today. There are many. Although A/MS standards have been passed, their proliferation has been painfully slow. Development of analog Intellectual Property (IP) and A/MS model libraries is still in the early stages. Verification strategies for A/MS design have yet to be completely defined (see "Wanted: Multilevel, Mixed-Signal Design Verification!" p. 112). Additionally, acceptance of A/MS design reuse in the industry is far from secure. And, these obstacles are just for starters!
Analog synthesis poses a unique obstacle for A/MS designers. The primary reason is that analog circuit design is a very complex task performed by only a select group of expert designers working at the transistor level. Compounding the problem is the fact that analog circuit behavior depends heavily upon the second-order effects on the transistor behavior. This means a large number of nonlinear specifications must be met over all process corners and operating conditions. As a result, the analog layout designer must be careful to avoid mismatching.
In other words, analog synthesis is critically dependent on layout. Furthermore, unlike digital synthesis, it's often a task performed manually—one transistor at a time—using the same techniques that have been used for years.
As the size of SoC designs crosses the multimillion-gate mark, this manual approach breaks down, making it necessary for designers to have a way of verifying that created behavioral elements match actual silicon. Also needed is an automated means of accurately and quickly converting mixed-signal, high-level models to equivalent transistor-level representations. The obvious solution is a synthesis-like tool that's appropriate for analog design.
Previous attempts at automating analog synthesis used generic algorithms to come up with novel architectures. Others tried to mimic the tiling concept from digital design. Each has met with only limited success, in part because they fail to transfer the transistor-level circuit knowledge to the tool. As a result, designers are still required to know a great deal about analog design at the transistor level.
Recently, several companies have come forward with alternative solutions. Those solutions fall into one of two categories: general analog synthesis, or nongeneral analog synthesis. The first approach is very straightforward. The tool takes in any high-level model and spits out an equivalent transistor representation. On the other hand, the nongeneral approach attempts to automate the creation of specific functional blocks. For example, a designer who wants an op amp would simply use one of these tools to choose the desired parameters. The tool would then create the block for the designer.
Some believe that the nongeneral approach falls short because it fails to offer a direct path to implementation. Designers must still figure out the design requirement/specification to be input into the implementation tools. This requires expert knowledge of the transistor level.
Advocates for the nongeneral approach, though, counter that general-purpose analog synthesis isn't the answer. Instead, they claim that there needs to be a focus on the design of widely used cells and functions, such as op amps, comparators, and CMOS spiral inductors. From these cells, special-purpose synthesis tools for larger analog and mixed-signal functions, like PLLs or ADCs, can be utilized to exploit the scalability of interior-point optimization methods.
Barcelona Design is one of the companies presently offering a nongeneral synthesis-based method for designing A/MS circuits. The Picasso Op-Amp Designer tool is geared toward designers in need of design circuits containing op-amp functions (Fig. 1). It automatically generates an optimized netlist from user-defined specifications for more than 50 types of op amps. A list of available op amps covers a wide range of performance parameters and foundry processes. The Dali RF Passives Designer provides synthesis, optimization, and simulation capabilities for the design of passive components, like inductors and resonators. Both tools are accessed via the web through a standard web browser.
Another synthesis solution comes courtesy of NeoLinear Inc. The NeoCircuit/NeoCell solutions provide both an open as well as a complete analog synthesis flow. In other words, these tools accept arbitrary analog circuit types for synthesis and can exploit the verification environment used by analog designers to judge the quality of evolving solutions. Each starts with a specification and ends up with GDSII.
In particular, NeoCircuit begins with an unsized schematic and employs the designer's existing simulation environment to numerically size and bias the circuit. NeoCell starts with a sized schematic, generates a placed and routed layout at shape-level, and handles critical geometric and electrical optimizations. A graphical analog-constraint editing environment allows essential analog information to be archived with the design and enforced during both circuit and physical synthesis.
Antrim Design System Inc. has a netlist synthesis solution, the Antrim MSS (Fig. 2). It allows designers to create, capture, and reuse complex analog and mixed-signal intellectual property. Antrim MSS also works to ease the burden of difficult technology migration for advanced IP.
Today, two plausible A/MS design language standards exist. They are the A/MS extensions to the popular VHDL, and the Verilog hardware description language standards. VHDL-A/MS has been certified as an IEEE standard, while Verilog-A/MS has been certified as an Open Verilog International (OVI) standard. Accellera—the organization resulting from the union of OVI and VHDL International—is now working to establish Verilog-A/MS as an IEEE standard as well.
While development of the A/MS design languages is certainly a notable accomplishment, an acceptable level of design automation in the A/MS arena will also require A/MS libraries. According to Roy McGuffin, president of Antrim Design Systems, "The early proponents of digital synthesis discovered that comprehensive IP libraries were essential to the automation flow. The same is true for analog synthesis." McGuffin remarks further, "Most A/MS libraries available today are hard and target particular foundries. Typically, the only representations available are a GDSII layout and a paper specification." McGuffin concludes, "For the libraries to be useful in an automation flow, they should include at minimum an accurate behavioral model in Verilog A/MS or VHDL A/MS."
In agreement is Dave Matty, president and CEO of NurLogic Design Inc. "The most important ingredients in a successful A/MS design flow are a rich set of analog parameters that have been very well characterized. This enables flexibility and optimum functionality," he states.
Essentially then, the implementation of a design reuse strategy is necessary. This strategy must be supported by libraries of portable analog IP, also known as virtual components (VC), like audio CODECs, ADCs and DACs, PLLs, and video interfaces. "The lack of tools enabling design reuse is a key stumbling block for automation of the analog/mixed-signal design flow," claims Mike Kondrat, vice president of marketing for Fluence Technology Inc. "One of the key methodologies that significantly enhanced digital design applications has been design reuse. This extremely important methodology is just beginning to be applied to mixed-signal design," he notes.
For an analog-centric design reuse methodology to be successful, the generation of portable IP must be enabled. With portable IP, the process of migrating A/MS designs to different fabs or manufacturing processes would be significantly streamlined. The need to begin a design from scratch every time it's ported to a new process would be eliminated too.
Kondrat points out that "as the electronics industry continues to divide into specialized vendors—design only, fab only, test only, etc.—the need for efficient, reliable methods of moving mixed-signal designs is becoming imperative." He goes on to explain how "mixed-signal circuits, by nature, require more validation than digital circuits when moving a design to a new fab or manufacturing process. Ultimately, this validation requires a large battery of SPICE-level simulations, which are extremely time consuming, to ensure that all performance specifications are met."
The Virtual Socket Interface Alliance (VSIA) is now working hard on specifications/standards that will help govern the creation, delivery, and portability of A/MS VCs for use in SoC designs. To date, the organization's A/MS working group has successfully released version 2 of its Analog/Mixed-Signal VSI Extension specification.
The specification provides a list of 60 deliverables (information) that a VC author must give to a VC integrator when exchanging a hard A/MS VC. The specification doesn't specify how to create or build the VC, but rather how to deliver it. It's currently in use by a number of companies and organizations.
In addition, VSIA is hoping to address the technical issues pertaining to the creation and delivery of IP in a very deep-submicron design environment. In particular, the company is now looking at the possible creation of standards and/or specifications to aid in dealing with such issues as signal integrity, design for test, and system-level modeling.
According to Henry Chang, chair of VSIA's Mixed-Signal Working Group, "Standardization efforts are extremely helpful because they codify best practices. This is the first step toward automation. As such," Chang claims, "an analog Virtual Socket Interface is critical to an SoC flow where mixed-signal IP is being used."
An effective A/MS design reuse strategy also requires a means for testing analog IP. The built-in-self-test (BIST) methodology may offer some aid through this challenge. By including BIST with the core, analog designs become much more portable. In many cases, BIST can even convert the analog signals to digital information, so they can be easily brought outside by implementing traditional digital design-for-test techniques, such as scan.
A number of standards efforts are under way to help with this issue. One example is the recently approved IEEE 1149.4 analog and mixed-signal boundary scan, or "dot4." This mixed-system testability standard enables chip developers to provide testable designs for very large mixed-signal devices. Additionally, exploration into the possibilities of developing a mixed-signal Standard Test Interface Language (STIL) extension to the IEEE 1450 STIL standard is in process. Furthermore, an IEEE committee is investigating test issues for IP.
At present, numerous companies offer analog IP for sale, as well as the tools to help in its creation and characterization. Antrim Design Systems, Dolphin Integration, Mentor Graphics Corp., and NurLogic Design are some examples of vendors offering model libraries and/or IP.
NurLogic, for instance, offers customers predesigned analog IP like PLLs, ADCs, and DACs. The company also sells the PromenADE suite of analog design elements, which features such MOS devices as diodes, resistors, and capacitors, in addition to specialty devices (Fig. 3).
Fluence Technology offers a tool for design characterization of mixed-signal and high-performance digital circuits. Known as DesignMaxx II, it automates the verification of circuits being retargeted to smaller geometries, different fabrication processes, and new applications (Fig. 4).
To a certain extent, development of an automated A/MS design flow requires recognition of the problems associated with having to combine both analog and digital functionality in complex SoC designs. Simulating both analog and digital functionality today, for example, often requires two different simulators. The preferable approach would simulate a design's analog and digital functionality together.
This dual simulation can be accomplished through one of two ways. The first is by employing a single-kernel simulator equipped with multiple algorithms to deal with both the analog and digital components of a design. The other method is by tying two simulators together to create a co-simulator using a backplane.
Today, a number of companies offer solutions utilizing each of these approaches. Nassda Corp., for instance, offers the HSIM full-chip hierarchical circuit simulator, while Avant! Corp. offers the StarMS analog and digital simulator. In addition, through its recent acquisition of Analogy, Avant! Corp. now offers Saber. This single-kernel-like simulator can read in Verilog and SPICE together.
Cadence Design Systems offers the Spectre circuit simulator for use on complex analog circuits, as well as the Accelerated Transistor-Level Simulator (ATS). A time-domain simulation/verification tool, ATS is specifically developed for very large, custom digital and mixed-signal circuits. Plus, the company's AMS Designer tool provides an environment in which to select and manipulate design input in preparation for simulation.
From Mentor Graphics, ADVance MS combines the ModelSim VHDL/Verilog simulator and the Eldo transistor-level simulator in one tool. With its co-simulation architecture, it allows the ModelSim solver to evaluate purely digital designs and lets a variety of analog algorithms evaluate portions of designs in SPICE and VHDL-AMS.
Synopsys Inc. offers ACE, an analog simulation option available for the TimeMill and PowerMill tools. A transistor-level simulation and power analysis tool, PowerMill has accuracy to within a few percent of SPICE.
Antrim's single-kernel offering is Antrim-A/MS. Using a multiple-solver solution, it applies simulation algorithms to different portions of a circuit for high performance and accuracy exceeding competing products.
Another option is the Multisim schematic capture and simulation tool by Electronics Workbench. Its co-simulation engine delivers fast, accurate simulation results for circuits containing any combination of SPICE/VHDL/Verilog modeled parts.
Another issue that must be addressed is integration of analog and digital blocks into a full chip. The main problem is the sensitivity of analog circuitry to things like noise. Unfortunately, digital circuits are very noisy. In order to deal with this issue, designers must learn to isolate and/or protect their analog blocks from any surrounding digital blocks. Automation tools can play a key role by not only identifying any potential problems, but also helping to point out quick fixes.
Luckily for designers, new tools under development promise to address the integration issue. SeismIC from CadMOS Design Technology Inc. is one of them. This substrate noise analyzer employs adaptive modeling techniques for accurate 3D substrate extraction. The extracted information is then analyzed for any potential problems.
Furthermore, physical synthesis must be resolved too. "Today's design strategies for the digital side of mixed-signal ICs depend on robust tools for cell-based logical and physical synthesis," explains Tom Beckley, president and CEO of NeoLinear Inc. "The circuit synthesis is necessary to transform schematics into correctly sized/biased circuits, while the physical synthesis transforms these circuits into masks."
Possible solutions in this area come from companies like Avant! Corp. through its new Cosmos environment, and Synopsys with its offering of AMPS. Designers can simultaneously optimize for power, speed, and area via AMPS. During prelayout, AMPS provides automatic optimization and identifies problem blocks by estimating interconnect effects. In post-layout it uses parasitics extracted from layout to determine whether or not design performance goals have been met.
Synopsys also offers PrimePower, a dynamic, full-chip power analysis tool for complex multimillion-gate ASICs. It's used to verify that designs meet power budgets and specifications, select the proper packaging, determine cooling requirements, and estimate the battery life for portable applications
It's a safe bet that within the course of the next few years, many of the obstacles related to the development of an automated A/MS design flow will be resolved. But when it's available, will designers want to use it? This is a fair question considering that most A/MS designers are a rare breed. As experts in their field, they relish the chance to manually craft a design. It's likely that the idea of this freedom being taken away through automation will be met with much skepticism and resentment. As the tools become smarter, though, and can more accurately accomplish specific tasks, this sentiment is bound to change. It will be helped along by the sheer size of complex SoCs, which are quickly making manual design techniques virtually archaic.
This will come as good news to engineering managers bent on keeping the design cycle moving. Considering the small pool of available A/MS designers today, it's easy to understand the lure of automation. If done properly, it will capture and leverage A/MS designer expertise. This means that even nonexpert designers will be able to design relatively complex analog blocks with minimal risk.
In an environment where getting your product to market ahead of the competition may make or break your company, benefits such as these are hard to overlook. Would you?
|Manufacturers Of Products Mentioned In This Report|
Antrim Design Systems Inc.
Cadence Design Systems
CadMOS Design Technology Inc.
+33 4 76 41 10 96
Fluence Technology Inc.
Mentor Graphics Corp.
NurLogic Design Inc.