A crisis of critical proportions is emerging as more and more IC designs demand a complex mix of digital and analog functionality to meet cost, size, packaging, power, and price considerations. This is a switch: in the past, most chips have been either digital or analog. And as a result, the underlying design and verification engines and flows used today are architected to handle contrasting requirements of either digital or analog/full-custom domains.
Addressing the new requirements of mixed-signal designs poses a number of challenges, starting with disparate databases and moving to conventional digital and analog design flows that cripple communication between the two realms. Compounding the challenge, these separate and distinct domains often are first introduced to each other during “chip finishing,” when analog and digital blocks are placed and routed together.
Chip finishing includes a number of tasks that occur at the end of the chip tapeout. Due to the absence of a common design environment, chip-finishing activities often fail to be reflected back into the original design, leading to major repeatability challenges for future generations of this design.
Well, what happened? While analog simulation has evolved through the sophistication of the underlying models and algorithms, today’s de facto standard analog/full-custom design tools originated from the early-to-mid-1990s. Although the core engines have evolved to meet increasingly complex design requirements, their underlying architectures are not fully capable of supporting a full-chip, mixed-signal design environment.
Amazingly enough, analog tools still support only minimal automation and analog designs are still largely handcrafted, which is a time-consuming and error-prone process. In fact, today’s analog design and verification tools are limited to capturing and simulating transistor-level schematics. And thus far, there has been limited success in automating the migration of an existing design to a new foundry or process/technology node. This is due primarily to the lack of a true integrated platform for mixed-signal design and to the issues related to legacy data migration. To do so with current tools effectively requires the circuit to be re-implemented from the ground up.
To be fair, the underlying architectures of these tools were never intended to support the sophisticated demands of a mixed-signal design environment and have served the design community reasonably well. Additionally, there will always be a segment of analog design that will need to be hand-crafted for performance reasons, just like microprocessor design in the digital world.
The obvious answer is the availability of an automated, full-chip mixed-signal design solution based on a unified digital and analog full-custom database that encompasses both analog and digital design and verification engines. This solution must provide capacity and performance. At the full-chip level, the environment must support automatic global routing for the chip-finishing stage of the design. And, it must support full-chip, mixed-signal extraction and simulation. For example, the ability to analyze a path that crosses the digital/custom boundary is a feature that every mixed-signal designer could use today.
The analog design tool must provide automation and productivity capabilities similar to its digital counterpart. Analog designers should be able to specify an analog function at a high level of abstraction. They need to work with tools that automatically synthesize this representation into its transistor-level equivalent and perform analog refinement and optimization.
A mixed-signal solution should have the capability to automate the migration process for an analog design from one process/technology node to another and from one foundry to another. It must support automated full-chip assembly, including global routing; full-chip LVS, DRC, and extraction; and full-chip verification.
In the long term, the analog/full-custom tool must be enhanced to support the capabilities standard in the digital world, such as automated placement, routing, and optimization—along with support for automated technology migration to new process nodes and foundries.
In addition to dramatically increasing productivity, an automated, full-chip, mixed-signal design solution will improve quality, reduce costs––particularly those associated with re-spinning failed implementations––and reduce time to market and time to profit.