One of the trickier aspects of system-on-a-chip (SoC) design is coming up with the bus structure for the circuit. Figuring out the best possible combination of bus masters, slaves, nodes, and layers is an arduous task that can make or break an SoC's overall performance.
But an enhancement to CoWare's N2C design system incorporates CoWare's second-generation Interface Synthesis technology. This helps users make intelligent tradeoffs for the best architecture for complex SoC buses.
In developing Interface Synthesis, CoWare collaborated with ARM and STMicroelectronics. The work with ARM verified that the tool performed properly with all aspects of the AMBA 2.0 bus specification.
The N2C allows designers to model their SoCs at a system level in C. To simulate bus configurations, designers must model the bus interconnect matrix (or crossbar switch). Hand-coding all of the bus interconnects isn't just tedious, it's also error-prone. The Interface Synthesis technology built into the N2C relieves the SoC architect from having to understand all of the messy details of the bus architecture.
Proprietary algorithms, configured by high-level user input, automatically synthesize bus-interconnect matrices. Within the N2C system are powerful analysis tools for checking the performance of different bus configurations. Designers simply resynthesize the matrix, simulate the design, and analyze the results. The tool can help sort out different protocols, arbitration types, multiple master and slave connections, and address decoding. For details, visit www.coware.com.