Cadence, Mentor Team To Open Up SystemVerilog Verification

Sept. 13, 2007

When the SystemVerilog hardware description language (HDL) came onto the scene a few years ago, it promised true openness and interoperability. Here, crowed the hype, was an HDL that would enable designers to build testbenches and capture them in verification IP (VIP) that could be reused time and again. Further, these verification testbenches and IP would be portable across platforms and distributed environments from various EDA vendors.

But the reality hasn't matched the hype, and SystemVerilog users have found themselves hurling invective at the EDA vendors, whose verification methodologies haven't enabled the kind of portability they promised. Finally, at least two major EDA vendors have decided that enough's enough.

Cadence Design Systems and Mentor Graphics will roll out the Open Verification Methodology (OVM), a joint tool-independent methodology for designers and verification engineers that promotes data portability and interoperability (see the figure). Within it are established interoperability mechanisms for VIP, transaction-level and RTL models, and full integration with other languages commonly used in production flows. The OVM will also include a robust class library and be available in source code format.

Cadence and Mentor have contributed both technology and resources to develop the foundation of the methodology and the libraries. The methodology will be made available under a standard open-source license, Apache License, Version 2.0. It's also backward-compatible with both companies' existing SystemVerilog verification methodologies.

"We both had a lot of common customers that were systems-oriented that wanted to go from block to system," said Dennis Brophy, director of strategic development for Mentor Graphics' Design Verification and Test Division.

With plans for a third-quarter rollout to early adopters as well as a production release in the fourth quarter, the companies still have work to do. More functionality will be added next year, for one thing. For another, decisions must be made on how to administer outside contributions.

Cadence Design Systems
www.cadence.com
Mentor Graphics
www.mentor.com

About the Author

David Maliniak | MWRF Executive Editor

In his long career in the B2B electronics-industry media, David Maliniak has held editorial roles as both generalist and specialist. As Components Editor and, later, as Editor in Chief of EE Product News, David gained breadth of experience in covering the industry at large. In serving as EDA/Test and Measurement Technology Editor at Electronic Design, he developed deep insight into those complex areas of technology. Most recently, David worked in technical marketing communications at Teledyne LeCroy. David earned a B.A. in journalism at New York University.