Electronic Design

Cadence Shoots For The Silicon Compiler Dream

It’s a long-held dream in the EDA industry: Into one end of the magic tool goes a high-level design representation of some kind, be it a functional specification a “golden” reference, or a collection of largely untimed models. Out of the other side comes a fully realized representation of the design at some lower level of abstraction, be it RTL or gate level, which achieves QoR at least equal to that achievable with hand coding in some fraction of the time.

We may not be quite at that level yet, having seen a number of attempts come and go. The latest effort, though, could prove a significant step in the right direction. Jumping back into the system-level fray, Cadence has released its C-to-Silicon Compiler, which it terms a next-generation high-level synthesis flow. Intended for creation of new IP initially, the C-to-Silicon Compiler is expected to eliminate many of the barriers to high-level synthesis. It’s fully integrated with Cadence’s established design and verification flows for maximum productivity.

There are several key elements to why Cadence believes its C-to-Silicon Compiler is a step forward in high-level synthesis. For one, previous generations of high-level synthesis technology have produced relatively poor results when presented with designs having mixed datapath and control logic. “With existing tools, some do a good job with datapath, while others do well with control logic,” says Ran Avinun, marketing group director for system design and verification at Cadence. “But there is no existing tool that we know of that is able to handle both kinds of structures. We’ve seen companies using two different tools for high-level synthesis, leaving them to hand-stitch together the datapath and control logic and to perform three separate verification processes.”

In the C-to-Silicon Compiler, this issue is addressed by what Cadence terms “embedded logic synthesis.” Because the Encounter RTL Compiler is built into the flow, the C-to-Silicon compiler provides accurate timing and area estimates in context. Rather than relying on pre-characterized libraries that already have had most of the major architectural decisions made, the C-to-Silicon Compiler flow enables designers to defer physical decisions for datapath and control logic so that they can be optimized concurrently and with understanding of the dependencies and interaction between them.

Another important aspect of the flow is incremental synthesis. Cadence’s Behavioral-Structure-Timing (BST) database provides for true incremental high-level synthesis. The BST database contains all design constraints as well as a collection of design-state snapshots. It records a full mapping of input source (C, C++, and/or SystemC) to generated RTL outputs. Armed with this database, users can perform “what-if” analysis using a function similar to the “undo” function in Microsoft Office applications. “If the user doesn’t like a decision the tool made for him, he can simply provide different constraints and force the tool to make a different decision,” says Avinun. “We record each step so when we make changes in the input, the tool knows what was done in the previous compilation and changes only the specific logic that’s required for the new changes.”

One of the barriers to adoption of high-level synthesis in the past has been the difficulties associated with retargeting or reusing design data. The C-to-Silicon Compiler flow allows for separation between design intent as regards functionality and the constraints used in the design. As a result, design files specify functionality throughout the design process and remain “golden” while the “directive” files (as Cadence terms them) specify constraints for timing, area, or application-specific parameters such as, for example, the bit width of a pipeline.

A final hurdle to adoption for high-level synthesis in the past has been poor verification support. The C-to-Silicon Compiler flow not only generates RTL, but also a fast hardware model that is functionally equivalent to the RTL as well as I/O cycle-accurate. These models, while not accurate enough for implementation, can be used to greatly accelerate simulation runs.

To complement the C-to-Silicon Compiler flow, Calypto Design Systems is rolling out a new version of its SLEC System-HLS (High Level Synthesis) tool. Based on Calypto’s sequential analysis technology, SLEC System-HLS verifies that the RTL code generated by C-to-Silicon Compiler is functionally equivalent to the original SystemC code. SLEC System-HLS comprehensively verifies the output of C-to-Silicon Compiler, eliminating the need for many time-consuming simulation regressions.

Additionally, Calypto’s PowerPro CG tool for RTL power optimization is already fully integrated with the Encounter RTL Compiler that underlies the C-to-Silicon Compiler flow. The integrated flow provides an automated, single-pass sequential analysis capability that produces optimized low-power implementations while still meeting design constraints.

The C-to-Silicon Compiler flow, including integration with the Calypto tools, will be demonstrated this week at Cadence’s CDNLive! user conference in Tokyo. The flow is in production now; contact Cadence directly for pricing information.

SLEC System-HLS is an added option to Calypto’s SLEC System. Each HLS vendor solution is sold separately and priced at $50,000 for a one-year, time-based license.



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