Calypto Design Systems’ PowerPro CG product for power reduction at the register transfer level (RTL) will support Si2’s Common Power Format 1.0 (CPF). Additionally, Calypto has joined the Si2’s Low-Power Coalition (LPC) to further work with customers and EDA vendors on improving interoperability between power optimization, design, and verification tools.
PowerPro CG (for Clock Gating) reduces power consumption by applying advanced sequential analysis techniques to identify micro-architectural changes that result in a lower-power circuit. It reduces design power by up to 60% with no impact on functionality, area, or performance.
Calypto Design Systems