Calypto Supports Common Power Format, Joins Low-Power Coalition

Calypto Design Systems’ PowerPro CG product for power reduction at the register transfer level (RTL) will support Si2’s Common Power Format 1.0 (CPF). Additionally, Calypto has joined the Si2’s Low-Power Coalition (LPC) to further work with customers and

David Maliniak

April 9, 2007

PowerPro CG (for Clock Gating) reduces power consumption by applying advanced sequential analysis techniques to identify micro-architectural changes that result in a lower-power circuit. It reduces design power by up to 60% with no impact on functionality, area, or performance.

Calypto Design Systems

www.calypto.com

About the Author

David Maliniak

MWRF Executive Editor

In his long career in the B2B electronics-industry media, David Maliniak has held editorial roles as both generalist and specialist. As Components Editor and, later, as Editor in Chief of EE Product News, David gained breadth of experience in covering the industry at large. In serving as EDA/Test and Measurement Technology Editor at Electronic Design, he developed deep insight into those complex areas of technology. Most recently, David worked in technical marketing communications at Teledyne LeCroy. David earned a B.A. in journalism at New York University.