Electronic Design

Challenges Lurk For 22-nm Physical Implementation

As difficult as the challenges of verification are at the 32- and 22-nm nodes, those of manufacturing a device with reasonable yields and reliability are perhaps even greater. Doing so will require an extremely sophisticated physical implementation environment that accounts for physical effects in the design loop as well as manufacturing variability in its optimization routines.

The manufacturing challenges also open up new EDA opportunities after tapeout and signoff, such as source-mask optimization and other computational lithography techniques that extend the life of fabrication equipment far beyond prior physical limits. In addition, developments like multilevel (3D) die packaging, through-silicon via (TSV) structures, and other non-traditional techniques for device scaling are pushing system and silicon design issues closer together.

The term “design for manufacturing” (DFM) reflects the need to consider manufacturing variability in design and to optimize for both functional and parametric yield. Yet it’s important to emphasize that DFM isn’t simply an additional tool or discrete step in the design process, but rather an integration of manufacturing-process information throughout the IC design and verification flow.

In 2009, more designers will be forced to migrate to a manufacturing-aware approach that extends across the entire design and verification life cycle, starting with cell library development and extending through place and route, physical verification, layout optimization, mask preparation, testing, and failure analysis.

A particularly difficult manufacturing challenge will come at 22 nm, when traditional equipment-based solutions enabling device scaling are no longer feasible due to engineering limitations on achievable scanner wavelength and numerical aperture. At 22 nm, traditional optical-proximity-correction (OPC) techniques and parametric shape optimization of source illumination won’t be enough to ensure high yield at such small dimensions.

Instead, the industry will have to look to computational lithography technology to take us to the next couple of process nodes. The next major improvement is called source-mask optimization, or SMO (see the figure). In this methodology, a “pixelated” source replaces predefined illuminator shapes, opening up an additional degree of freedom in computational lithography.

As in the past, the objective is to create beneficial interference patterns. But with a pixilated source, the illumination shape is virtually unconstrained. This means each specific design going through the fab can have a custom-tailored illumination pattern, optimized to provide a maximum process window for the specific design.

To enable source and mask optimization, computational algorithms and methods for optimizing both source and mask, pixel by pixel, will be developed. Equally important will be the selection and development of the appropriate compute platform to provide the computational capacity and speed required to suit it for production usage.

Physical Prototyping Trends
The coming months and years will see a renewed interest in physical prototyping of IC designs. This will serve the need for feasibility validation of projects earlier in the design process, coupled with the increased search for implementation options that will result in power and/or cost benefits.

In the past, a relatively easily accomplished process shrink brought these gains. But below 65 nm, such scaling is painfully difficult. So floorplanning will come back into vogue in a big way in the form of structured, efficient “path finding” exploration and optimization methodologies. 

Another trend is the emergence of 3D silicon, with the advent of viable TSV technologies that will lead to a number of new EDA and silicon products. TSV technology offers incredible savings in power and quantum availability of memory bandwidth at the point of need in large systems-on-a-chip (SoCs). With it, SoC architects can quickly develop multiple product variants with varying degrees of memory sizes and types, all of which can be customized at build time based on predefined “plugs and sockets” or TSVs. 

Looking beyond the die itself, there will be greater need to cross chip, package, and board boundaries to effectively manage design issues such as signal integrity, power integrity, and electromagnetic interference (EMI). Chips that function properly in isolation can often fail when packaged and/or board-mounted.

Designers will be forced to examine noise and power margins on a broader level that encompasses the chip, package, and board to effectively manage timing and signal-integrity closure. This will also entail cross-team collaboration with tools that facilitate real-time and incremental collaboration between widely geographically dispersed individuals and teams.

Finally, the growing analog content in SoCs demands a more fleshed-out reuse methodology for analog IP, particularly when it comes to process portability. Look for an increased emphasis on technologies to achieve this aim (see “Automating Analog IP Process Migration,” ED Online 20478).

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