Laker custom
System 9.1
ECO cycle
As 28-nm process technologies start to hit their stride, design teams have begun the predictable round of fretting over whether EDA vendors’ tools will be up to the tasks at hand. It’s not as if you can blame them, either. The size and complexity of system-on-a-chip (SoC) designs mean there’s even less margin for error. Meanwhile, runtimes for tools throughout the flow are exploding.
Fortunately, there have been numerous bright spots over the course of 2010, and many of them are focused in the implementation segment of the design flow. This year’s crop of Best in EDA are aimed squarely at easing designers’ worries about advanced process nodes.
Database Gets Support
A particular area of concern is custom IC layout, which is a time-consuming, painstaking task that challenges both designers and their layout tools. In the latest iteration of its Laker custom-IC layout system, SpringSoft has added support for the OpenAccess database and application-programming interface (API) from Si2. From a purely business perspective, there are a few advantages to any tool having support for OpenAccess, which enables the creation of parallel flows without proprietary lock-in.
The other compelling business driver behind the use of OpenAccess (Fig. 1) is interoperability. It enables designers to incorporate tools from other vendors who support OpenAccess or to use in-house tools crafted for particular purposes.
Through OpenAccess, Laker supports the IPL Alliance’s interoperable process design-kit (PDK) libraries. This effort seeks to establish an interoperable ecosystem in custom design. SpringSoft reports that it has performed extensive interoperability testing with OpenAccess-enabled tools from Magma, Ciranova, and Synopsys to ensure that the exchange of data is seamless.
As to the details of Laker’s integration with OpenAccess, SpringSoft says that Laker is the only tool in its class that supports all three of the possible interfaces with third-party tools: file exchanges, data exchanges, and a tightly coupled runtime model. The runtime model is the most sophisticated of the three, in which multiple applications can share the same memory without having to open and close the applications. The net result is that the tools all look like they’re part of the same environment.
Other enhancements to the Laker system include a new custom row placer and custom digital router. Both work directly in Laker with no need for the timesink of environment switching. Also, no data-translation or compatibility issues are involved. Together, the placer and router are wire-length driven and work with smaller designs of 50,000 fixed-height standard/custom cells.
The tools support advanced process technologies, with 28-nm support planned by the end of 2010. They provide routing for power and ground layers for complete design support. Laker performs a hybrid approach to routing, performing first a fast gridded route. After doing design-rule checking, the tool then switches to a shape-based route that yields a DRC-clean (design rule checking) output with a high completion rate.
A TRULY MODERN FLOW
The consumer electronics market largely determines the demand for high-end SoCs. Applications such as cloud computing are driving those demands higher. The problem for design teams is that there’s a gap between what they’re attempting to achieve in terms of device complexity and density and what EDA tools can provide.
In its Encounter Digital Implementation (EDI) System 9.1, Cadence Design Systems has raised the bar in terms of what a modern implementation flow can deliver. Most notably, EDI System 9.1 enables the creation of designs that are two to three times larger than its predecessor could achieve through a hierarchical, high-capacity prototyping flow.
At the 32- and 28-nm nodes, the total cost for large designs is expected to approach $100 million. Missing a market window by six months for a respin could mean a potential loss of $5 billion in profits.
EDI System 9.1 is intended to help designers avoid these missteps in several ways. For one, its floorplanning and prototyping flow allows automatic and concurrent examination of hundreds of design variables. This way, designers can quickly find an optimal architecture for their SoC.
Cadence calls EDI System 9.1 a next-generation SoC implementation system (Fig. 2). It’s intended to streamline and tightly integrate floorplanning and prototyping with place and route and signoff. It offers very high capacity for design exploration fueled by Cadence’s data abstraction modeling. The system performs automated floorplan synthesis with concurrent cell and macro placement.
The system also improves design predictability and convergence through fully integrated signoff analysis. In addition to the timing, signal integrity, and power analysis engines already integrated into Encounter, Cadence added silicon-accurate turbo extraction. The result, Cadence says, is a flow with virtually no iterations and greatly improved quality of results (QoR).
Finally, in terms of design for manufacturing (DFM), EDI System 9.1 supports all 32- and 28-nm requirements for routing and design rule checking (DRC). Cadence’s Encounter DFM lithography hotspot fixing, incorporated within EDI System 9.1, screens the design during routing for areas that could become hotspots in silicon. It then automatically finds and repairs these areas.
Easing The Pain Of STA
Static timing analysis (STA) is used throughout chip design. It’s employed for the creation of basic constraints in synthesis, for block- and chip-level timing closure in physical implementation and for engineering change order (ECO) analysis and final timing signoff prior to physical verification and tapeout.
While design complexity has skyrocketed in recent years, STA has remained largely static. Design teams must now analyze hundreds of corner cases stemming from the number of operating modes in portable devices.
These factors translate into numerous pain points for STA users, most of which center around runtime and capacity issues. Another associated issue is the need to spend on larger servers and multiple licenses. With the release of its Tekton static timing analyzer, Magma Design Automation has attempted to address all of these issues in one fell swoop.
Centered on a next-generation architecture, Tekton more efficiently handles on-chip variation (OCV), composite current-source models, and crosstalk analysis. A key capability is its multi-mode/multi-corner (MM/MC) analysis technology, which enables users to run a large number of STA scenarios on one machine.
Tekton performs fast and accurate what-if analysis for engineering change orders. It can be used in such scenarios along with Tekton QCP, a high-capacity full-chip extraction platform that enables MC extraction with minimal increases in runtime.
With the combination of Tekton and Tekton QCP, designers can change their netlist and get very quick extraction feedback on how the changes impact timing. Further, Tekton is tightly correlated to existing signoff tools. It has Magma’s FineSim Spice simulation built in as well for even more accuracy enhancement.
Extraction is an important part of any flow, but it becomes critically important in the later stages for ECO analysis. In a flow with Tekton, because the QCP extractor runs at the same time, netlist changes are responded to with instant feedback on how timing is affected. As a result, the ECO cycle (Fig. 3) is less fraught with iterations and is much faster.
Magma makes a very bold claim for Tekton, which is that any design can be timed in less than one hour. One benchmark involved a design of 1 million instances, for which 12 scenarios were analyzed. With both crosstalk and on-chip variation analysis in force, this design took just 13.4 minutes of runtime. A design with 11.4 million instances ran in 41 minutes on a single-CPU machine and in just 8.8 minutes on an eight-core machine.
The architecture is fully multi-threaded, resulting in orders-of-magnitude improvements in runtime without having to invest in multiple licenses or large costly servers. Magma’s benchmarks have shown that scaling is almost linear with up to 24 CPUs.