Gone are the days when "just get it right" summed up the job. Today, chips have to be right, cheap, and done yesterday. When developers search for shortcuts, they invariably choose the path of least resistance.
To save time and mitigate risk, design teams gravitate toward familiar intellectual-property (IP) and process options and opt for the "free libraries" or "generic" fabrication technology. But as teams migrate to shrinking technology nodes, technical decisions become more daunting with farreaching economic implications.
For instance, modern 130- and 90-nm fabs and ASIC vendors often offer a dozen process variants in one technology node, each tuned for a specific specification like density, speed, or leakage. Further, some IP providers offer dozens of standard-cell and memory library variants optimized for key attributes, such as low power and high performance. Designers must determine the precise combination of process and IP options to successfully meet their design goals and, secondarily, assess what kind of deltas can be expected between these varying options.
A generic 130-nm process with a "free" IP library is very tempting. But designers may not be aware that cell libraries alone can vary in key metrics, such as leakage, by up to an order of magnitude. Designers also may want to consider that density can vary by as much as 50% and power by as much as 150%. Depending on the end goals of the specific application in which they're working, there are some key issues for designers to consider.
In the wireless space, consider processes and libraries optimized for power and leakage—what often are called low-leakage, low-power, and low-voltage process variants. Some options effectively reduce overall power, but they may increase leakage significantly—and vice versa. And, using threshold voltage blending may further reduce leakage while keeping performance high.
In the high-speed networking industry, consider high-performance cells, memories, and process variants, often called " highspeed" or "over-drive" by vendors. Yet it's important to assess the power impact of such libraries and processes early in the design flow to avoid IR drop and costly thermally enhanced packaging technology if possible.
In the consumer space, where price is key, consider high-or ultra-high-density IP. High volumes may dictate the use of smaller technology nodes like 90 or even 65 nm to reduce unit cost. Keep a close eye on leakage in these technologies, as well as potentially astronomical nonrecurringengineering (NRE) costs. Re-spinning masks in 90 nm can cost four times more than an entire mask set in 180 nm.
No matter what the end application, consider strategies such as using multiple standard-cell libraries on the same die. Also consider each hierarchical block an individual design for the purposes of IP selection. And, consider using voltage scaling or block power-down strategies to reduce power consumption during various functional states.
There has been an explosion in foundry process and IP options at 130 and 90 nm. The only way to effectively manage the chaos is to use the scientific method. Design teams must spend more time at the architectural stages of the design flow, even prior to register transfer level (RTL) design, to consider the economic and technical impact of early chip architectural decisions.
Early decisions about your node, process, and library can have huge functional and economic ramifications. It's important to consider not only die size and costs, but also package, test, assembly, and NRE costs. For example, even if you can meet your goals for yielded die cost, your chip's power requirements may force you to use a package that makes your final price point nonviable.
The solution is a well-defined architectural exploration and estimation process. Evaluate technology nodes, processes, and IP options early in the design flow, and determine the optimal set of options to meet functional and performance goals while still bringing your chip to market profitably.
