Electronic Design
Co-Design Reliability Relies On Sound Validation Approaches

Co-Design Reliability Relies On Sound Validation Approaches



1 of Enlarge image



Materials inputs to a model are critical factors in ensuring that outputs make physical sense and are reliable to guide designs (see “Cultivate A Model Of Success In Co-Design” at www.electronicdesign.com). But to guarantee the proper construction of models, incorporation of the appropriate physics that describe the phenomenon, and elimination of erroneous simplifications, it’s also important to validate the models through correlations to physical measurements.

Thermomechanical-Modeling Validation 

Thermomechanical stresses emerge when materials of different expansions in an assembly go through a temperature cycle. Localized displacements of a structure develop as materials proceed through this cycle, leading to strains and stresses. These displacements turn into easily observable warpage or bow in a package, offsets between a die and a substrate, and deformed solder joints.

Modeling tools can directly output these displacements. Therefore, by executing appropriate measurements of the displacements, it’s possible to make validation comparisons directly to the model values.

Many tools exist for measuring thermomechanical model validation. Perhaps the most common is shadow moiré. Shadow-moiré testing projects a shadow grid on a device’s surface from a grating (Fig. 1). The object’s surface bow distorts the projection. A camera mounted above the package images fringes caused by interference between the distorted image and the original grating.

Software in the shadow-moiré tool analyzes the distortions to produce a map of vertical displacements (Fig. 2). Here, the colors on the plot represent the displacement from a flat plane, a result of the thermomechanical stresses in the package. The warpage across a diagonal of a package is then compared between a model’s output and the shadow-moiré measurement (Fig. 3)

As can be seen in the figures, the match is not exact. That’s because real-world devices experience warpage variability due to materials, geometrical, and manufacturing tolerances. With the shadow-moiré tool, parts and, subsequently, model validation can be tested over a wide temperature range. 

Digital image correlation (DIC) is another tool used to validate thermomechanical models. With DIC, a computer notes specific features in an image at a specific temperature. When there’s a change in the sample’s temperature, the computer notes the changed locations of the features. X,Y displacements between the various locations are plotted, producing a strain image that can be compared to the modeled values.

One advantage of DIC is its ability to observe a very small field of view (in the micron range). Comparably, shadow-moiré measurements typically range over multiple millimeters. As a result, modeling engineers have a chance to verify the smallest details of their model when employing DIC. For example, it enables the observation of a package cross-section to detect the surface motion of a die compared to the substrate below.

An alternative to DIC uses a cast-in-place micro-moiré grating. Observations of changes in the grating with temperature shifts enable calculations of displacements and strains.  However, some art is required to form an appropriate molded grating. Thus, the advent of powerful DIC has led to the diminished usage of micro moiré.

Shadow moiré or DIC will sometimes be used to identify the zero-stress temperatures of an assembly. If only two materials are laminated together, the zero-stress temperature represents the temperature at which no bow occurs in the assembly. Unfortunately, in the case of a package, multiple materials are usually laminated together at different temperatures. As a result, there may not be a single temperature at which each package component is at zero stress.

Diffused silicon strain gauges can help identify the zero-stress temperature for chips in the package. With strain gauges, the zero-stress condition is taken as the stress in wafer form. After packaging these strain gauges, stresses on the chip cause changes in the strain-gauge resistance. When calibrated, these resistance shifts enable back-calculation of the stress in the silicon.

The package temperature can be raised or lowered until the silicon is at zero stress, establishing the zero-stress temperature. It’s important that strain gauges be temperature-compensated so shifts caused by temperature coefficients of resistance aren’t confused for stress shifts.

Indirect validation is often required to validate reliability predictions. For example, thermomechanical models usually correlate modeled strain energy density in solders to the number of cycles to failure. The strain energy density doesn’t capture the complete physics of the solders. As a result, this number must be correlated to cycles to fail under the assumption that the strain energy density captures a portion of the physics.

To validate the thermomechanical model, actual packages are tested to failure and compared to the model’s prediction. A curve fit relates the calculated strain energy density to the number of cycles to failure. Fitting a number of models to various package reliability results will ultimately establish a correlation.

Thermal-Modeling Validation 

There are multiple ways to validate thermal-model results. The most common method is to use a test die with power-dissipation elements (resistors). A temperature sensor on the die (or multiple sensors) responds to temperature shifts, enabling calculation of the die temperature. Die temperatures measured at different power dissipations then can be compared directly to package models in the same test configuration, providing a direct comparison of model error.

Another common validation approach utilizes an infrared (IR) imaging camera to sense a package’s or system’s surface temperatures. These temperatures are then compared to the models. No specialized test die are required for this technique.

To get accurate temperature readings, the IR camera must be emissivity-corrected. For example, a polished metal surface emits less IR energy for a given temperature than a polymer (e.g., a mold compound or solder mask) emits at the same temperature. If the IR camera isn’t emissivity-corrected, it may report a cooler temperature for the polished metal surface compared to the polymer surface, even when they’re at the same temperature. IR “gun” measuring devices have proven to be less accurate, because they average temperature across their field of view and sometimes don’t allow for emissivity correction.

Thermocouples offer a simple, inexpensive method for determining surface temperatures. Unfortunately, thermocouples aren’t very accurate when used on electronic package surfaces—the thermocouples themselves act as heatsinks, reducing the surface temperatures they’re trying to measure. This becomes particularly evident when the thermocouple is mounted to a plastic package surface. Generally, the plastic’s thermal conductivity is much lower than that of the thermocouple.

So, how much error can occur? In one case involving a small plastic package, an individual trying to establish a system-level operating temperature used a thermocouple that created a 25°C drop compared to the “non-heatsinked” surface.

A thermocouple approach requires that best practices be followed. The thermocouple must be of very fine gauge, 36 or 40. The bead of the thermocouple should be as small as possible and attached to the surface with a thermally conductive epoxy bead of minimum size. The thermocouple should be dressed along the IC component and printed-circuit-board surface as much as possible to minimize thermal gradients in the thermocouple at the measurement location. Dressing the thermocouple against the surface will reduce its heatsinking efficiency.

Electrical-Modeling Validation

Electrical models can be used to predict crosstalk, power and ground bounce, the filtering effects of capacitors, and other factors. Using appropriate instrumentation, these phenomena can be directly measured on input and output pins and compared to the modeled results.

When making very high-speed electrical measurements, one must take great care with instrument setup to ensure impedance mismatches, cable lengths, connector insertion points, and other systematic issues don’t obscure the desired results. The test set has to be “de-embedded” from the measurements to compare the signal of interest directly to the modeled values. This process may require quite a bit of fine-tuning in the electrical system. The system can sometimes be debugged with specially designed substrate test structures, or even by using complex test die with active drivers.

Specific examples of electrical-model outputs that can be validated through testing include measuring the impedance of specific structures.1 In this case, a network analyzer was used to measure predicted impedances. Comparing the model to the measurements showed the need to improve the models by applying lossy characteristics, as well as highlighting specific frequency limits of the models. 

Another useful technique for package model correlation takes advantage of time-domain reflectometer (TDR) measurements. A TDR launches a signal into a specific pin and delivers a measurement of reflections that occur at impedance transitions. The delay time and intensity of these measured reflections can be matched against models.

Electrical models are often validated against other electrical models. That’s because certain types of linear solvers (e.g., full-field finite element codes) are verified multiple times, but end up being too compute-resource-intensive to use routinely on today’s complex package structures. Many times, faster algorithms will be employed to capture the complexity by simplifying some physics of the problem. To prove the efficacy of faster codes, modeling is performed on just a few package structures using the full physics codes. Then, those results get compared to models made with faster algorithms.

In summary, co-design modeling validation results have become essential in proving the validity of the models. Once there’s validation of a modeling approach, it can be applied over a wide range of problems with confidence. Without validation, co-design outputs sometimes are no more than just pretty pictures. The diligent co-design engineer will be anxious to validate ever more modeling cases, thereby building confidence in the co-design results.

Acknowledgement: The author gratefully thanks Dr. Masazumi Amagai for the shadow moiré images used in this article.


  1. S. Li, et.al., “Development and Validation of a Microcontroller Model for EMC,” Electromagnetic Compatibility Europe, 2008.
Hide comments


  • Allowed HTML tags: <em> <strong> <blockquote> <br> <p>

Plain text

  • No HTML tags allowed.
  • Web page addresses and e-mail addresses turn into links automatically.
  • Lines and paragraphs break automatically.