Wireless Systems Design

Co-Verification In Action

In an ASIC design for a satellite ground receiving station, Hughes Network Systems encountered a problem. Its device was designed to receive packets that were transmitted from a satellite. It would then convert those packets to Internet Protocol (IP). But the Hughes team discovered that a bus-arbitration problem was causing packet loss. Bus-arbitration priorities were set in a way that allowed the CPU to dominate the bus, thereby preventing hardware buffer access to a de-queuing bus. As a result, the packets failed to be transferred to memory and the buffers overloaded. Packets were then dropped.

Usually, problems of this sort require weeks of tossing the problem back and forth between hardware and firmware teams. But in this case, there wasn't enough time for RTL simulation to conclusively identify the error before tapeout. Using a hardware/software co-verification tool like Mentor Graphics' Seamless, the Hughes engineers were able to work on the problem while sitting side by side. They debugged and corrected the errors in a matter of hours.

In the same design, Hughes discovered that a hand-off wasn't occurring on the initialization of an encryption register. Instead, the encryption register was initializing in the middle of performing a calculation. Using the co-verification tool, the design team had excellent debug visibility much earlier in the design flow. It successfully facilitated the debug of the register-initialization error using the tool's software debugger and a virtual prototype of the hardware.

Because of its ability to quickly and accurately co-simulate hardware and software, the co-verification tool also permitted the Hughes team to enhance the design validation. As a result, they gained a high degree of confidence that tapeout would deliver a working design. The tool even identified hardware errors in the RTL code that weren't detected by logic simulation. Ultimately, using the tool kept the project within its schedule constraints and helped the design team avoid post-tapeout errors. Normally, such errors would have required a very costly and time-consuming ASIC respin.

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