Finite State Machine path query, event coverage and partial design instrumentation have all been added to the latest version of SureCov, the firm's code coverage analysis software for integrated circuit (IC) and intellectual property (IP) design. Available in volume shipments for Windows NT, SunOS and Solaris, as well as HP workstations running HP-UX, the software analyzes Verilog RTL design descriptions and measures the coverage for all possible code blocks, arcs, expressions, events, FSM states, and state transitions. The latest version adds FSM path query functionality to allow the designer to identify a path through the FSM and to query the database to evaluate coverage of the path.With this implementation, the designer, through the GUI, selects states in the path of interest on the state diagram. SureCov produces the state diagram after automatically recognizing and extracting the FSM for the RTL source. It does a real-time query of the coverage database as the designer is selecting the path.