Electronic Design

Compiler Attempts To Address The Timing Closure Challenge

Achieving timing closure with today's complex IC designs is quite a challenge. In fact, it may be one of the most daunting tasks designers are faced with. While a number of solutions to this problem have emerged, none has managed to garner widespread industry approval. Synopsys, however, has entered the fray with a tool that promises to help designers meet timing closure and get the best possible performance out of their designs at the same time.

This new tool, Physical Compiler, specifically targets both front-end and back-end designers. It works by allowing register-transfer-level (RTL) designers to output a placement that's guaranteed to meet timing. With its RTL-to-placed-gates capability, users can achieve the shortest path to post-route timing closure as well as high circuit performance.

Because the tool addresses highly complex IC designs, it has a multimillion-gate capacity limit, effectively able to represent about 350k placeable objects (over a million gates) comfortably in a 2-Gbyte process size. Additionally, the tool supports both flat and hierarchical designs and offers a global routing capability.

The Physical Compiler's primary benefit is its elimination of the need for wire load models and iterations between logical and physical design. Since it interfaces to industry-standard routers, the tool can be easily plugged into any of today's design methodologies.

Physical Compiler is built on Synopsys' unified logical and physical database. It incorporates the company's patent-pending FlexPlace placement technology and proprietary congestion minimization algorithms. At the heart of the tool lies the PhysOpt engine, which unifies these technologies and simultaneously optimizes for all of the design cost functions.

In other words, the Physical Compiler tool effectively unifies synthesis and placement. This ultimately creates a shift in the way integrated-circuit design at 0.18 µ>m and smaller is accomplished. The end result is that final placement can be moved farther up to the front end of the circuit design process.

Physical Compiler is part of Synopsys' physical synthesis top-down design methodology solution, which also includes the Chip Architect and FlexRoute tools released in 1999. It's based on Synopsys' Liberty Physical Libraries, and it offers LEF support via a translator. The product is currently in limited availability on the Sun Solaris platform. It will be available for general release in April on multiple platforms, including Solaris, HP, and RS6000. Contact the company directly for all pricing information.

Synopsys Inc., 700 East Middlefield Rd., Mountain View, CA 94043; (650) 584-5000; Internet: www.synopsys.com.

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