Startup CebaTech's first product, the C2R Compiler, is touted as the first C-to-RTL compiler capable of working efficiently on large, complex designs at a high level of abstraction and then automating the process of creating high-performance hardware solutions. The tool enables full-chip designs to be architected, verified, and implemented using ANSI C as the design language in a flow that is two to three times faster than using the traditional RTL-based design approach.
The C2R Compiler generates synthesizable Verilog RTL from untimed ANSI C. Hardware architecture is defined in the C source code, which remains the golden source throughout the design flow. Software engineers working with hardware architects can rapidly create accelerated hardware implementations of software algorithms to meet performance, cost, and power requirements.
CebaTech's C-based ESL design methodology and C2R Compiler allow fast changes to the system architecture, enabling extensive exploration of design tradeoffs to achieve the optimal design. In addition, the CebaTech flow allows functional verification of the hardware design to be performed in native C software environments, eliminating the dependence on RTL simulation, speeding up the verification process and lowering costs.
At least one beta user, Agora Laboratories, has been using the C2R Compiler to take a legacy G.7xx audio codec, as well as the MPEG-4 video compression algorithm, into hardware. According to Agora, the tool's extensive support of ANSI C syntax allows leveraging of existing C code bases with minimal changes. With the compiler, Agora has been able to quickly develop FPGA prototypes to demonstrate accelerated hardware to potential clients.
The C2R Compiler is available now for FPGA and ASIC designs. U.S. pricing starts at $145,000. For more information, visit www.cebatech.com.