Electronic Design

Complexity Woes Need An Abstraction Reaction

The future of both design and verification is looking up—in an abstract way. The complexity of both the hardware and software will compel designers of complex systems-on-a-chip (SoCs) targeting 90- or 65-nm processes to move into the electronic system-level (ESL) domain—that is, if it hasn't already. In 2007, many more design teams will leave the safe and familiar harbor of the register-transfer level (RTL) and begin the design process at a higher level of abstraction.

For some designers, the process is beginning at extremely high levels of abstraction, as in the algorithmic level. More design teams now realize that entering the design process at the algorithmic level can profoundly affect their results. Look for greater amounts of tools and technologies to facilitate design at the algorithmic level in 2007, including multiple synthesis options for taking algorithms down to more concrete levels of abstraction.

One of the hottest topics at last year's Design Automation Conference involved virtual platforms for early architectural exploration, as well as hardware modeling for use in software design. This will surely continue into the new year. Lots of room for innovation remains within the platform-based design space, though (see "Getting EDA Back On Track With Platform Innovation").

The Emergence Of MPSoC
Designers are embracing the multiprocessor SoC (MPSoC) concept because processor clock frequencies have leveled off at between 3 and 4 GHz (or 1 to 2 GHz in the embedded realm). Instruction-level parallelism is one way to improve performance, but that, too, is running out of steam. Meanwhile, the marketplace craves performance from end products, with more features in smaller packages with lower power.

But this adds a significant wrinkle if you're contemplating an MPSoC approach, particularly from a software perspective. The hardware design is fairly well understood, but exploiting parallelism on the software side is less so. Developing parallelized software that's mapped to and optimized for MPSoCs is a challenge in itself.

Furthermore, verification of the application's functionality will become largely a software problem. A new class of tools and technologies must emerge reflecting a changed verification dynamic. Expect this trend to unfold in 2007.

EDA flows are already beginning to recognize that hardware and software engineers approach their worlds in very different ways. Hardware designers crave sequentialism, while software designers seek parallelism. However, hardware and software flows themselves increasingly subdivide into specialized disciplines.

In 2007, these subdivisions, such as "custom logic design" and "processorbased platform design" in the hardware realm and "application software" for control processors and "device software" for specialized processors (e.g., DSPs) in the software arena, will begin to converge into more streamlined methodologies. The industry will see the continued emergence of flows that allow multi-specialist team cooperation that spans design groups, companies, and even discrete industries.

Parallelism Prevails
Finding ways to exploit parallelism will soon prove to be a key differentiator between, say, one chip for the H.264 video coding standard and another. Architectural exploration and the ability to rapidly evaluate different approaches will become critical within the design process. This demands sophisticated techniques for creating application-level parallelism to feed MPSoCs that move and manage vast flows of traffic at lightning speeds.

Even as design flows evolve toward higher abstraction levels, at no time in the foreseeable future will designers be able to bypass the RTL stage of the process. And even though ESL methodologies can help manage complexity, it's also critically important that flows can create RTL that matches the transaction-level models used to kickstart software design. It's still only then that the decisions made in the ESL domain can be validated.

Power is an unavoidable design constraint that will become more crucial than ever as 65-nm processes go mainstream. Tools and flows that consider power from the earliest stages of ESL architectural exploration will evolve into essential elements of SoC design (see the figure).

Moreover, look for further development in the Power Forward Initiative, a conglomeration of EDA vendors, intellectual-property providers, system houses, and foundries. The group has proposed the Common Power Format, an open specification language that captures all power-specific design, constraint, and functionality requirements, such as multisupply voltage and power shutoff, in a single file.

In addition, SystemVerilog's adoption will deepen, entrenching it as the dominant language for automated testbench methodologies. With the support of more sophisticated verification engines, SystemVerilog-enabled techniques such as assertions, constrained-random data generation, and functional coverage will be requirements in 2007.

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