Electronic Design

Composite Current Models Gain Support On TSMC 65-nm Process

Composite Current Source (CCS) models are now available for use in the TSMC 65-nm and 90-nm process technologies. Used in conjunction with the Synopsys Galaxy Design Platform, the high-accuracy CCS timing and noise models allow the designer to reduce guardband margins during design implementation and sign-off, thus improving quality of results and reducing design iterations. CCS models are proven to deliver signoff-level accuracy to within 2% of HSpice simulation as seen at leading semiconductor companies.

CCS modeling technology, part of the open-source Liberty library modeling standard, enables highly accurate and comprehensive modeling of nanometer effects that encompass timing, signal integrity, and power. CCS modeling technology constitutes the foundation for modeling variations. CCS models are designed to be scalable for voltage, temperature and process. They enable voltage variation modeling, simplifying advanced low-power design flows such as multi-Vt and multi-Vdd, as well as dynamic voltage and frequency scaling. CCS model libraries are available from leading foundries, intellectual property (IP) vendors and integrated device manufacturers (IDMs).

The TSMC standard-cell libraries — enabled with CCS modeling technology for the 65G+ and 65LP as well as the 90G, 90GT and 90LP processes — are available immediately through the Synopsys DesignWare library at no additional cost to current licensees. Visit Synopsys and TSMC.

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