As noted in the book's foreword, functional verification has been described by the authors of the 2003 International Technology Roadmap for Semiconductors (ITRS) as having become "a bottleneck that has now reached crisis proportions." In Comprehensive Functional Verification, the authors seek to address the various stages of the verification process through hands-on exercises based on RTL implementations of a four-function calculator.
Copiously illustrated with charts, tables, flow diagrams, and code examples, the book begins with an introduction to verification and the verification flow, the fundamentals of simulation-based verification, and how to formulate a verification plan. Part II homes in closely on simulation, covering testbenches and checking, as well as verification reuse. Of note is the discussion of coverage, a much-misunderstood topic that is increasingly critical to verification success. Part III emphasizes formal verification, a technology that's gaining in favor despite the desire of many verification engineers to avoid it. Once designs are complex enough, there's no avoiding formal any more, and this book will help you come to grips with formal technology and how it fits into an overall verification strategy.
Part IV covers comprehensive verification, including completion of the verification cycle and advanced techniques such as high-level modeling. Finally, part V brings case studies, and it's here that the authors share some of their personal failures and successes, and what made them so.
Verification is an ever-changing discipline, and the authors are right up to date with the latest techniques, languages, and methodologies. There's considerable discussion of assertion-based verification, one of the field's hottest topics, and of the latest verification languages such as the Property Specification Language. Overall, there's much to learn here for both beginners and veterans.
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