With architectural exploration at high levels of abstraction becoming of greater interest to ASIC designers, it's crucial for these designers to have a means of coverifying hardware and software at those levels. So, Mentor Graphics is extending its Seamless coverification environment with C-Bridge technology, which will permit the incorporation of C/C++ hardware descriptions, testbenches, and protocol models into Seamless sessions.
With C-Bridge, designers can use Seamless to coverify hardware and software earlier than ever in the embedded design process and before key blocks are coded at the register-transfer level (RTL). The environment supports mixed C, C++, and hardware description language (HDL) simulation.
Modeling at levels above RTL lets designers quickly code up flexible prototypes. In the Seamless environment, hardware and test-related constructs can be described in C for smooth incorporation into a design composed of C and RTL blocks. Nothing precludes the use of any appropriate C-language constructs or reuse of legacy C models. Also, C-Bridge supports Open SystemC.
The benefit of C modeling is, of course, faster logic simulation that enables more software to be run against the hardware architecture. C-Bridge allows areas of the RTL design not critical to a given verification run to be modeled in C and still be part of the verification. As verification goals and targets shift, the mix of RTL and C can be altered to keep the simulation runs moving along at a decent speed.
Seamless with C-Bridge is available now as part of the Seamless 4.3 release. Pricing starts at $60,000.
Mentor Graphics Corp., www.mentor.com/seamless; (503) 685-7000.
