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CoWoS, 20nm Reference Flows Usher In Next-Gen Chip Designs

CoWoS, 20nm Reference Flows Usher In Next-Gen Chip Designs

74638-AAmsterdam, The Netherlands: TSMC recently demonstrated two foundry-first reference flows that support 20nm and CoWoS (Chip on Wafer on Substrate) technologies. The 20nm reference flow enables 20nm design with double-patterning-technology (DPT) aware capabilities to reduce design complexity and deliver required accuracy. DPT enablement includes pre-colouring capability, new RC extraction methodology, DPT sign-off, physical verification, and design for manufacturing (DFM).

The CoWoS reference flow enables 3D IC multi-die integration. It will allow for a smooth transition to 3D IC without having to make wholesale changes to existing methodologies, according to TSMC. It includes place-and-route management of bumps, pads, interconnections, and C4 bumps; innovative combo-bump structure; accurate extraction and signal integrity analysis of high-speed interconnects between dies; thermal analysis from chip to package to system; and an integrated 3D testing methodology for die-level and stacking-level tests.

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