EE Product News

CPLDs Offer 50% Die Size Reduction

Using an advanced FastFLASH process technology from United Semiconductor Corp. of Taiwan that is said to offer more than a 50% die size reduction when compared to the initial 0.6-micron process, XC95144 CPLDs, with a 7.5-ns pin-to-pin speed and 144 macrocells, is said to address the designer's need in the density sweet spot of the CPLD market. The newest member completes the XC9500 CPLD family with densities ranging from 36 to 288 macrocells in a variety of packages. The XC9500 family features an architecture optimized for pin-locking, a necessity for designers who want to take advantage of in-system programming for easier prototyping, simpler manufacturing, and remote equipment upgrades.

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