Intended for signal routing and interface logic design with in-system programmability, the ispGDX80A, ispGDX120A and ispGDX160 comprise a family of 5V generic crosspoint devices. The ispGDX80A architecture consists of 80 special-purpose programmable I/O cells interconnected by a Global Routing Pool (GRP) that minimizes signal delays and delivers high performance. The device offers any-input-to-any-output signals delays of 5 ns, clock-to-output delays of 5 ns, and operating frequencies up to 111 MHz. Other features include a 4:1 high-speed input mulitplexer, registered outputs, three-state or open-drain output options, IEEE 1149.1 Boundary Scan Test logic, ispJTAG in-system programming and PCI compatible outputs. Packaging is a 100-pin TQFP. The ispGDX family is optimized for digital signal interface and routing applications, and are a class of programmable devices distinct from CPLDs and FPGAs.