Electronic Design

Custom Sources Light Way To 22-nm IC Lithography

Concern is rising about the ability of today’s microlithography equipment to scale below 45-nm design rules and still print with acceptable fidelity. There are different schools of thought on how best to meet this challenge—some more hardwarecentric, others more software-centric, and still others combining elements of both. Thus, there has been a spate of announcements of late in this arena (see “IBM And Mentor Graphics Team Up On 22-nm Computational Lithography” at www.electronicdesign.com, ED Online 19974).

Now, yet another effort to smooth over the inadequacies of conventional microlithography comes from Cadence Design Systems and Tessera Technologies, who have teamed to devise a custom approach to source-mask optimization for the 22-nm node. The best illumination map for a given design layout may or may not be represented in the library of standard sources that comes with today’s 192-nm scanners. Cadence and Tessera contend that there must be co-optimization of both the scanner’s illumination source and the photomasks themselves to maximize yields at 22 nm.

Consequently, the two companies are pairing to deliver a comprehensive source/mask optimization methodology (see the figure). There are two primary pieces to the puzzle. First, Cadence’s Source/Mask Optimizer (SMO) software takes in a set of “layout clips,” which are critical structures in the layout that must print within the process window to deliver the proper electrical characteristics. These clips are fed to the tool’s SMO engine. Other inputs to the engine include the depth of focus you’re trying to achieve as well as the dose latitude, the pitch, the placement, and the critical-dimension (CD) control parameters.

In this methodology, the companies claim, process engineers won’t have to wait until they run optical proximity correction (OPC) tools until problems in the layout’s printability are exposed. The parameters are fed into the tool upfront along with an initial OPC model, and the tool provides an optimum illumination map. The new capability is integrated into the Cadence resolution enhancement technology (RET) flow for both single- and double-patterning lithography, and it delivers exceptional ease of use and automation to accelerate both technology development and production ramps.

A key differentiation of the Cadence technology is its ability to optimize the lithography source illumination based on the printability of two-dimensional layout structures through a process window, rather than just through critical dimension (CD) requirements of the design. The Cadence source mask optimization solution is also applicable to both conventional and free-form illumination patterns.

Tessera comes in through its Digital Optics Corp. subsidiary, which manufactures controlled angle diffusers for scanners. Optical lithography equipment typically comes with a library of standard diffusers that provide specific illumination patterns (such as circular, annular, or dipole) for exposure of the photoresist on a wafer. At larger process technology nodes, these standard patterns may have been sufficient. But at advanced nodes like 22 nm, it’s likely that a completely arbitrary, custom diffuser will be required to broaden the process window for a given layout.

Cadence will work with Tessera to validate the output of the SMO engine, verifying that the customized illumination map that's produced by the tool is consistent with the manufacturability of such diffusers and is not simply a theoretical solution that cannot be produced.




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