As time passes, more bits and pieces of the electronic-system-level (ESL) design and verification flow come together. If you’re a fan of ESL methodologies, and in particular of Bluespec’s tools and flavor of Verilog, you may wish to visit this year’s 44th Design Automation Conference to check out the latest additions to Bluespec’s library of pre-packaged IP and design reuse capabilities.
In adding bus-fabric components and transactors to its AzureIP Foundation Library of verified IP, Bluespec seeks to reduce the stress placed on the SoC design flow by the complexity and concurrency demands of bus fabrics. The new blocks include bus-component libraries for ARM’s AMBA AXI and AHB protocols, as well as for the Open Core Protocol (OCP)-IP interface. Components include parametrized bus structures, bus-interface transactors, and data-type libraries.
Falling between low-level IP components (e.g., adders and multipliers) and large IP blocks (e.g., Ethernet, PCI, H.264, and processors), these blocks fill a void in the middle of the IP space. This is the area used most often by internal design teams, but inadequately addressed with current IP due to the level of customization required for each application.
With the AzureIP bus-fabric libraries, modelers and designers can quickly and correctly create and connect to bus-fabric interfaces and channels compliant with industry-standard bus and communication protocols. At the heart of Bluespec’s bus-fabric IP offering is a transaction-level-modeling (TLM2) bus payload data structure and protocol. This generic representation supports multiple bus protocols and is based on the Open SystemC Initiative (OSCI) TLM 2.0 draft specification. Use of the TLM2 representation allows designers to work with bus interactions on a transaction level for high-level modeling or efficient hardware implementation. Details of each bus-specific signaling protocol are encapsulated within library building blocks, eliminating the need to be re-designed and re-verified each time a design includes channels or interfaces based on that protocol.
For each supported bus protocol, the associated AzureIP package includes:
* A master transactor, which converts a stream of TLM2 operation descriptors, communicated through transaction-level GET/PUT interfaces, into a sequence of protocol-specific bus operations; * A slave transactor, which converts a sequence of protocol-specific bus operations into a stream of TLM2 operation descriptors, communicated through transaction-level GET/PUT interfaces. * A bus-fabric constructor, which is a module constructor that, given a set of master and slave interfaces, creates the complete bus fabric and any associated arbiters as required.
Bluespec implemented these bus-fabric components and transactors in such a way as to facilitate design reuse. Because the AzureIP package components are implemented natively in Bluespec source code, they don’t represent fixed modules with a few, pre-selected degrees of parametrization. Instead, each package component represents a design template, which is automatically transformed by the Bluespec compiler into a specific instantiation that’s parametrized and optimized to the specific application context of each use. Unused capabilities are automatically removed, saving power and area as compared to the results that can be achieved using more traditional hardware IP.
As the TLM2 structure is common to different bus structures, entire designs can be completed and verified independent of the specific bus protocol selected for each interface or communication channel. This allows a single design to be used in multiple applications, each time using a different set of selected bus protocols. Such flexibility also allows designers to postpone decisions regarding which protocol to use until late in the design cycle.
The AzureIP Foundation Libraries are included as part of Bluespec’s ESL software. Design services are available to further accelerate system modeling and implementation.
Note that the OCP International Partnership (OCP-IP), the consortium that administers the support, promotion, and enhancement of the Open Core Protocol (OCP) specification itself, will exhibit at DAC with freshly minted white papers to distribute. One covers network-on-chip (NoC) benchmarking, while another covers the subject of interface debug. OCP-IP will also debut version 2.2 of its SystemC/OCP transaction-level models. In addition, the organization will detail Toshiba’s use of OCP in its Super Companion chip.
Bluespec (DAC Booth #6963)
OCP-IP (DAC Booth #4363)