It’s true that the RTL design flow is largely commoditized. Yet, EDA vendors do still manage to come up with at least incremental gains for their tools and flows. If you’re in search of time/cost savings, greater productivity, more efficient and accurate modeling, or any of a number of enhancements, gold could be laying in wait for you somewhere on the DAC show floor.
Making its public debut at DAC, Envision Technology will demonstrate its "design for power" approach to reducing power consumption by up to 50%. Interested parties can contact [email protected] to pre-register for a demo session.
The Envision power-aware approach embeds intelligence into the design with digital sensors that can adapt as power requirements change. The Envision semiconductor IP can be automatically inserted during the RTL-to-gate-level design process to activate and deactivate circuits in real time based on their state of activity and power needs at any given cycle.
Envision’s digital sensor IP is supported with a suite of fully automatic and manual interfaces, and is implemented using EDA-style configuration and partitioning tools that fit seamlessly into existing RTL tool flows. No software or gate-level changes are required, and the functionality is automatically integrated as a Verilog-based "black box" with minimal impact on design size and performance. Run time for configuring the IP is typically only a few minutes, and the resulting netlist can be verified with standard simulation tools. Initial benchmarks have shown less than 5% area penalty for achieving up to 50% power reduction through the use of Envision’s patented sensing technology.
If gains in analog/mixed-signal modeling are important to you, check out Lynguent’s ModLyng Integrated Modeling Environment. ModLyng is claimed to yield productivity improvements for engineers who develop and maintain analog/mixed-signal (AMS) models. It is language- and platform-independent and yet compatible with the most widely used AMS simulation tools and environments.
Engineers use ModLyng to create AMS models from scratch or to maintain, debug, or enhance imported legacy models written in Verilog-A/AMS, VHDL-AMS, or MAST. Models can then be exported to any of the aforementioned HDLs; thus, a model may be migrated from one HDL to another. All product capabilities are graphical or equation-based in nature, so engineers focus on developing the features and behaviors of their model while ModLyng deals with the complexities of correct HDL expression and construction.
ModLyng may be used to manage both semiconductor device models and behavioral models of higher-level AMS functional blocks.
ModLyng is currently available to select beta test sites; general release is planned for September 2007. ModLyng is configurable with different options. A typical configuration is licensed for $35,000 per user, per year.
A pair of vexing SoC design issues, namely power-gating analysis (PGA) and simultaneous switching noise (SSN), are now being addressed by Sequence Design’s CoolTime with automated analysis capabilities that enable faster, more accurate power signoff. The new PGA and SSN capabilities address critical design issues in low-power wireless and high-speed interface designs, power reduction, and noise immunity for designs like DDR. These capabilities are available as options to CoolTime.
Power gating is a powerful leakage-reduction technique, but is difficult to analyze and design. CoolTime offers a fast "what-if" PGA capability that enables users to rapidly determine switch turn-on sequences for controlling peak rush currents and minimizing wake-up times due to power gating. CoolTime PGA examines the peak current required by a gated block as it turns on, and calculates the impact of this current on the power grid to other active sections of the chip. CoolTime PGA also analyzes wake-up times to determine how long it takes for instances in the power-gated block to reach the nominal supply voltage and be function and timing ready. CoolTime’s PGA capability provides what-if rush current and wake-up time analysis results in an hour or less.
When multiple output drivers switch simultaneously, they induce a voltage drop in the chip/package power distribution. This simultaneous switching momentarily reduces the supply voltage and raises the ground voltage within the device relative to the system power and ground. This shift in potential is known as SSN. Many designs in high-volume applications, such as storage, computing, and communications, are impacted by SSN, including those with high-speed parallel interfaces (DDR), or highly inductive or high-pin-density packaging.
CoolTime now analyzes and determines SSN with enhanced designer productivity and increased silicon integrity through the use of accurate internal die parasitics assembled from extraction. It provides accurate on-chip parasitic extraction and automates the entire analysis, reducing the time to prepare the netlist from a week to a few hours. For the user-defined region of the pad ring, it generates chip parasitics, applies parasitic reduction, determines I/O instances in the region, sensitizes I/O instance pins, stitches all Spice components (including package model), and loads results in CoolTime’s waveform viewer.
The PGA and SSN options for CoolTime will see production in the third quarter of 2007. Pricing for the options begins at $90,000 each for a one-year license.
Sequence Design is also using DAC as the springboard for a way to help SoC designers reduce power early in the design cycle. PowerTheater-Explorer is an option to PowerTheater, Sequence’s power-analysis engine, which allows more engineers access to PowerTheater for maximum cost-effectiveness. Using PowerTheater-Explorer, designers can pin down hotspots in the design and visualize, debug, and interactively determine ways to reduce a design’s power consumption.
With PowerTheater-Explorer, the RTL power tree display, for example, shows hotspots in the design that can be cross-probed to schematics showing connectivity. It will indicate how activity is moving through the design and how instances impact one another in terms of power. These results can be displayed and analyzed at RTL, gate, or mixed RTL-gate levels of abstraction.
In addition, because the design data is stored in the industry-standard Open Access database, PowerTheater-Explorer allows designers to write their own power-data analyzers and reporting algorithms.
Scheduled for production in the third quarter, PowerTheater-Explorer costs $30,000 for a one-year license.
Silicon Navigator will demonstrate its Rocket Design Environment (RDE), which now offers additional options: a schematic editor, RTL power analysis, and SKILL-compatible PCells. RDE includes tools that CAD developers can use to speed the adoption of the OpenAccess database and customize a design cockpit. It offers a desktop and graphical user interfaces (GUIs), data and script viewers, and application programming interfaces (APIs). It can be used standalone or in conjunction with other commercial OpenAccess environments. It’s available now for licensing.
IP quality is an issue of concern for the industry, especially as more designers turn to design reuse as a means of saving time and gaining efficiency in their overall design cycles. To that end, the VSI Alliance (VSIA) will conduct a training session at DAC to give attendees some familiarity with its recently released Quality IP (QIP) Metric version 3.0. The QIP Metric now includes vendor assessments as well as soft-IP, hard-IP, and verification-IP extensions.
At the training session, to be held at noon on Tuesday, June 5 (Room 32AB, San Diego Convention Center), representatives of Mentor Graphics will provide an overview of the QIP Metric. Also, Denali Software personnel will provide a step-by-step walk through on how to complete the Metric for an IP core. The session will be wrapped up with comments on the QIP Metric from users at LSI Logic. A free lunch will be provided for attendees at the session.
In other IP-related news, Chip Estimate, the marketer of IC-planning tools, will be on hand at DAC to provide details on its Prime IP Partner program. Two new members of the program are Kilopass Technology and CebaTech. Both IP vendors’ wares can now be explored at www.chipestimate.com, Chip Estimate’s free online facility searches IP offerings; search results can be used to plan forthcoming IC designs with the company’s InCyte tool.
As a Prime IP Partner, Kilopass is adding data about the company’s embedded nonvolatile memory (NVM) IP to the ChipEstimate.com database. Similarly, CebaTech will provide access to information regarding its CebaIP platform and CebaIP cores.
Atrenta will be at DAC to show its Spyglass family of tools for early design analysis and early implementation, with booth demonstrations of Spyglass, SpyGlass Power, SpyGlass Constraints, SpyGlass CDC, and SpyGlass DFT. All of Atrenta’s SpyGlass tools are aimed at delivering earlier design closure in various domains. Atrenta will also demonstrate its 1Team:Implement tool for architectural exploration.
The SpyGlass RTL analyzer detects, debugs and corrects design issues at the source, thereby ensuring high-quality RTL. Demos at DAC will walk you through a series of steps to ensure that a design complies with HDL coding standards, coding styles, synthesis, simulation, verification, connectivity, finite-state machine, clock, and reset issues.
SpyGlass Power enables a low-power methodology at the RTL, early gate-level, and late gate-level design stages. It can be used for power estimation, reduction, and verification.
SpyGlass Constraints can help with timing closure through generation, management, and verification of design constraints, including false and multicycle paths. At DAC, Atrenta will demonstrate new capabilities for generation of timing-critical false paths from RTL and incremental creation of SDC components.
Spyglass CDC identifies clock-domain-crossing (CDC) issues and ensures that clock synchronization is correct. It automatically recognizes and formally verifies most complex clock-synchronization schemes. DAC demos will cover structural CDC analysis, which includes recognition of synchronization schemes like multi-flops, FIFOs, and handshakes. Atrenta will also show how to formally prove the correctness of synchronizers, including gray-coding, data-hold, and reconvergence.
SpyGlass DFT is intended to help attain testability goals at RTL. The tool identifies causes for poor test coverage and helps fix these issues. It also provides an accurate estimate of test coverage at RTL with a correlation of 1% to 2% with automatic test-pattern-generation (ATPG) tools. In demos at DAC, you can learn how to make RTL scannable, make latches transparent, add test points, and validate scan chains.
With 1Team:Implement, chip architects and RTL designers can explore the feasibility of their design rapidly and accurately. The architecture exploration enables early prototyping of design specs and lets chip architects assess the impact of architectural tradeoffs. As an RTL prototyping environment, the tool allows early predictability of timing and congestion issues and provides directed guidance to RTL designers for meeting area, timing, and power goals. Demos will show how to perform architectural tradeoffs, make microarchitectural changes, and automatically generate and evaluate multiple floorplans. You can also learn how to cross-probe from the schematic, timing, and physical views directly to the RTL source to pinpoint the source of potential problems.
Envision Technology (DAC Booth #2893)
Lynguent (DAC Booth #2165)
Sequence Design (DAC Booth #4860)
Silicon Navigator (DAC Booth #2179)
VSIA
Chip Estimate (DAC Booth #2464)
Kilopass Technology (DAC Booth #3263)
CebaTech
Atrenta (DAC Booth #6082)