Electronic Design

DAC Preview: Physical Design And Analysis

There’s no doubt that design for manufacturing (DFM) tools and methodologies will make some of the biggest splashes at the 43rd DAC. But more broadly speaking, implementation tools will abound at the show.

Sagantec (booth 3326) will debut a tool that physically implements front-end DFM analysis. Tentatively called "DFM-Fix," the tool corrects lithographically-induced hot spots so that chip designers can send a clean, manufacturable design to the mask makers. The tool uses lithography analysis and physical design optimization technology to correct data in the GDS stage. These corrections are then verified before going to final verification by the signoff MRC tool.

An ecosystem for support of data-driven DFM methodologies will be shown by TSMC at their booth 3263. The ecosystem hinges on a manufacturing-based unified data format that channels DFM capabilities through selected EDA tools. The format aligns lithography process check (LPC), chemical/mechanical polishing (CMP) analysis, and critical-area analysis (CAA) tools to TSMC’s manufacturing data format. This enables designers to use the same DFM data file irrespective of the tool or vendor. It also enables simplified use, management, and updates to DFM analyses using these tools. Designers can download an encrypted TSMC DFM data kit and run TSMC-qualified tools directly on their workstations, obtaining results that are consistent with TSMC’s own internal DFM results.

Pyxis Technology (booth 2323) is a startup focused on routing of designs at very advanced process nodes (65 and 45 nm). They’ll attempt to address DFM issues through what they’re terming correct-for-manufacturing design. Rather than fixing problems after routing, Pyxis’ technology takes into account lithography, yield, and CMP issues during the routing process. Part of the answer lies in a DFM-aware architecture, as well as with an ecosystem of partners. Pyxis will demonstrate its DFM routing technology along with its DFM partners, all of whom have settled on the OpenAccess database and application programming interface (API).

For Ponte Solutions (booth 2204), DAC will hinge on its yield-sensitivity analysis tool for nanometer designs. Yield Analyzer is based on the concept of unified models of mission-critical yield issues for designers of cell libraries, memories, IP, or block- or chip-level designs. Yield Analyzer delivers a model-based analysis system with actual fab-correlated models.

The OASIS data format, which is expected to replace GDSII, is championed by OASIS Tooling. In booth 3051, DAC attendees can see demonstrations of the broader capabilities of the OASIS format. Some of the demonstrations will show that OASIS is more than a file-transfer format.

On the power-analysis front, Sequence Design (booth 1614) will show updates and enhancements to its PowerTheater, CoolTime, CoolCheck, and CoolPower tools. PowerTheater now supports clock-gating predictions, enabling users to accurately predict the effects of clock gating on their designs. CoolPower also offers analysis of clock-network power consumption, with quick analysis of the full clock tree to determine whether design changes have resulted in power savings.

Targeted at 65-nm designs, Azuro’s PowerCentric tool for clock implementation (booth 1928) includes features to support variability-aware power reduction, as well as support for designs with multiple voltage islands. The tool assembles patent-pending approaches to clock-tree synthesis; clock-gate logic synthesis; and accurate, average-case, vectorless dynamic power analysis.

An automatic means of closing timing in multi-mode/multi-corner designs will be shown by Manhattan Routing in booth 3349. MRI’s latest version of Physical Window/Optimization Cockpit (PW/OC) won’t replace the manual analysis and optimization that the tool was originally designed to perform. But running an automatic optimization step before doing any manual work can enable many more timing violations to be addressed automatically.

For analog/mixed-signal designers, Kimotion Technologies’ tool suite (booth 2302) uses proprietary characterization, optimization, and model-generation technologies to allow mixed-signal designs to be verified across environmental and statistical process variations. The suite is based on 15 years of research at the Catholic University at Leuven, Belgium.

On the library front, ViASIC (booth 1108) will highlight its DuoMask library. The two-mask, via-configured standard metal library can be used to build structured ASICs or as a fabric for developing rapidly configurable sections of an SoC. Via masks 2 and 4 are used for configuration in a seven-mask process.

And on the test side, Advantest Technology Solutions (booth 3043) will demonstrate its CertiMAX product, which enables event-based semiconductor validation using a PXI-based environment without imposing the limitations of cycle-based test. The product allows functional verification, debug, and characterization of first silicon without deviating from the design environment. Chip designers can take a standard .vcd file from a simulation tool and use it as is on silicon. By enabling design data to be used directly without requiring vector, timing, or format translation, CertiMAX simplifies the validation process.

For much more on implementation tools and technologies at DAC, check the July 6 issue and its full DAC preview at www.elecdesign.com, ED Online 12943

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