Two areas of the design flow seem to be the ripest for innovation going forward. One is the electronic system level (ESL) at levels of abstraction higher than RTL, and the other is the physical domain, where the ongoing migration to process nodes below 90 nm is placing undue stress on silicon yields. This year’s 44th DAC will be a hotbed of news with regard to the back-end flow.
The increase in analog and mixed-signal (AMS) content of systems on a chip (SoCs) and ICs is causing a disproportionate number of chip respins. At the same time, verifying circuit performance in a mixed-signal environment is becoming more complex and more critical to yield and cost control. At DAC, Kimotion Technologies Inc. will unveil a technology that allows AMS circuit and system designers to build performance models that deliver much more thorough optimization and verification of yield and performance issues than is possible with existing verification flows.
The transition from traditional corner-based design methodologies to flows using detailed statistical distributions of individual technology variables, coupled with the integration of analog and digital parts on a single chip, has pushed the need for technology that automatically verifies and optimizes a circuit’s yield across statistical process variations. Process variability and shrinking supply voltages combine to reduce voltage headroom and make AMS circuits more sensitive to fluctuations in process and environment.
The traditional way to verify the robustness of AMS designs over process and environment variations is to run a Monte Carlo analysis on transistor-level descriptions. In contrast to this relatively slow and inefficient approach, Kimotion’s technology allows circuit designers to model, verify, and optimize their analog/mixed-signal circuits. Models can be built incrementally to a desired level of accuracy with a very small number of simulations. They can be used either in a classic Monte Carlo flow, replacing the simulations, or by Kimotion’s verification and optimization technology. This helps designers not only identify potential problems before going to silicon, but also correct them.
Chief among physical concerns at sub-90-nm process nodes is power and leakage control. Apache Design Solutions will be at DAC with its RedHawk-ALP, a physical power-integrity tool for advanced low-power and leakage-control designs. RedHawk-ALP targets power savings and leakage-control techniques used in 65- and 45-nm designs, including VTCMOS (variable-threshold CMOS) circuits with substrate back-biasing, power-gated memories and custom macros, and on-chip low-dropout (LDO) voltage regulators.
VTCMOS is a relatively new circuit technique for reducing leakage current. It dynamically alters the substrate voltage. However, varying of the substrate voltage introduces noise on the supply source and increases variability in circuit behavior. RedHawk-ALP accurately extracts bias networks and analyzes full-chip dynamic power integrity including instance-based Vsub(t) and Isub(t) for design tradeoff analysis.
MTCMOS, or power gating, has been widely used for reducing leakage by controlling the on/off switching of logic blocks or cells in 90- and 65-nm designs. As designs move toward 45 nm, designers must add power switches to memories and custom IP to further reduce leakage. RedHawk-ALP expands the modeling capabilities and simulation capacity of the existing cell- and block-level MTCMOS support to handle large GDS-based custom macros.
On-chip LDOs are often used to deliver the desired voltages to different parts of the chip (voltage islands) without introducing extra power pins. Since an LDO is an analog circuit with a continuous output-voltage waveform, designers have traditionally used Spice to simulate its behavior. At the full-chip level, LDOs are typically modeled as an ideal voltage source, which hides the potential power noise generated by the LDO circuit. RedHawk-ALP accurately models LDO circuits and reveals the true transient behavior for full-chip power noise analysis.
RedHawk-ALP is available for beta evaluation now and will be available for production use in the third quarter of 2007. Annual licenses start at $330,000; existing licensees of Apache’s RedHawk-LP product can upgrade to RedHawk-ALP.
As process technologies migrate to 65 and 45 nm, it’s increasingly difficult to preserve design intent and to ensure that GDSII layouts are indeed manufacturable with acceptable yields. Creation of a high-yield, full-chip layout presupposes a high-yield library. Physical cell layouts must be optimized early in the design cycle to mitigate defect mechanisms, such as random defects, gate variations, contrast, and others, as well as many other foundry-specific yield-loss mechanisms, manufacturers, and foundries, as well as library and IP providers.
Takumi Technology’s Enhance is a comprehensive layout inspection, rating, and repair system that can detect and quantify layout problems. It does so based on multiple defect criteria, both those defined by Takumi and those defined by the user. For each problem the tool identifies, it can assign a failure rate in parts-per-billion to each problem location. Further, a cost can be assigned to each failure location so that meaningful tradeoffs between various problems can be defined.
Essentially, Takumi Enhance can take an imperfect cell library and use the foundry’s manufacturing data to enhance that library to deliver improved yields and device performance. It allows designers to geometrically and lithographically analyze a given layout using multiple yield-loss mechanisms to detect, rate, and repair locations that are potential yield-loss hotspots.
Kimotion Technologies (DAC Booth #7382)
Apache Design Solutions (DAC Booth #6382)
Takumi Technology (DAC Booth #6969)