As it assembles for this year's 42nd Design Automation Conference in Anaheim (June 13-17, www.dac.com), the EDA industry finds itself at a crossroads. Disparaged by some as out of touch with designers' needs and falling down in attempts to lead the design community deeper into the submicron realm, the EDA industry sorely needs a "home run," a technological coup that will shore up its image.
DAC is the likeliest place for such a coup to emerge. Over 10,000 attendees will experience an exhibition by over 225 vendors of EDA tools, technology, methodologies, services, intellectual property (IP), and more. The technical program features sessions on all aspects of IC design: low-power design, design for manufacturing, embedded hardware and applications, interconnect and signal integrity, verification, simulation, reconfigurable devices, and high-level synthesis. Attendees can choose from among 13 tutorials, four workshops, 18 DAC Pavilion presentations, and 57 technical sessions.
DAC often reveals industry trends, giving industry watchers an inside track on where EDA is heading. This year's DAC figures won't be a disappointment.
One burgeoning trend is electronic-system-level (ESL) design, or design at an abstraction level higher than RTL. Startups, established players, and everyone in between seem to be jumping on the ESL bandwagon.
Synfora will show the 5.01 release of its PICO Express application-engine synthesis tool for system-on-a-chip (SoC) design. The new release features enhanced capabilities for algorithms in application areas such as multimedia (H.264), imaging, wireless (3GPP), and security. The tool creates flow-controlled networks of hardware accelerators from sequential C algorithms.
At DAC, Synfora also will present its Aspen architecture, a highly tuned, configurable embedded processor. Aspen is a key element of the company's second application synthesis engine product, scheduled for release later in 2005. The architecture is highly parallel and supports features such as programmable interrupts, direct connection to internal registers, and streaming data. At DAC, Synfora will demonstrate the Aspen architecture integrated with PICO Express accelerators using an H.264 video encoder.
A number of entries in the ESL space are trying to give designers a quick route from a design's behavioral description to implementation. For example, Bluespec is adding cosimulation capabilities to its compiler and simulator. As a result, IC designers can use Bluespec's cycle-accurate C models in SystemC or SystemVerilog modeling environments. In addition, the company will announce multiple clock-domain support with integrated formal clock verification. By incorporating clocking into the semantic model, Bluespec's tools will ensure proper clock connectivity when the design is synthesized.
Mentor Graphics made a splash at last year's DAC with its Catapult C algorithmic synthesis tool. This year, it'll roll out extensions to Catapult C for automatic creation of SystemC transaction-level models (TLMs) and wrappers. As a result, designers will be able to rapidly explore architectural tradeoffs and simulate their designs from 20 to 100 times faster than with traditional RTL simulation environments. Catapult C will automatically add SystemC hardware details to C++ algorithmic models to generate cycle- and bit-accurate SystemC models.
The latest version of Celoxica's DK Design Suite, which uses Handel-C to implement an ESL flow for algorithmic acceleration, sports an extended feature set for greater algorithm acceleration. Version 4.0 of the DK Design Suite can synthesize larger designs more quickly thanks to advanced memory-utilization technology. From Handel-C algorithms, it automatically generates RTL that's optimized for Design Compiler to better support structured-ASIC and SoC physical design flows.
Celoxica also will show its RC10 programmable platform for ESL training, design evaluation, and rapid prototyping. Fitted with a high-density FPGA, the board features Virtual Peripherals that enable applications programmed into the FPGA to connect to PC-hosted Ethernet and video resources.
There's growing support for the Mathworks' Matlab language, particularly in the DSP arena. IP is a key element of algorithmic synthesis of DSPs. To that end, AccelChip will show the 2005.1 release of its AccelWare IP toolkits and DSP Synthesis tool (Fig. 1). The latest version of the cores contain Cholesky matrix factorization and matrix inversion. Enhanced cores support BCH encoding and decoding as well as scrambling and descrambling.
AccelChip's 2005.1 version of DSP Synthesis provides a Matlab/Simulink design flow for DSP implementation in FPGAs. The tool offers a direct path to Xilinx's System Generator by automatically generating verified System Generator IP blocks from floating-point Matlab models.
To some designers, it's important to work with an ESL tool vendor that offers a direct path into implementation. Synopsys is among the few EDA vendors in the market that can make such a claim. The company created a unified ESL-to-RTL design and verification flow to ensure a predictable path from ESL through to silicon (Fig. 2). For Synopsys, such a flow is based on its System Studio tool for algorithm and SystemC-based architecture design and analysis. SystemStudio offers tight integration with the VCS simulator as well as a transaction-level interface with Vera.
Some designers are looking for a flow from ESL all the way to implementation. Others need early evaluation of architectural decisions and knowledge of how those decisions affect performance. CoFluent Design, a first-time DAC exhibitor, will demonstrate a pre-release version of its CoFluent Studio v1.1.
Earlier versions of this ESL toolset supported only a single performance index--resource usage. Version 1.1 supports power consumption, memory footprint, and cost. Each index can be observed and analyzed at all levels of the system's hierarchical structure, locally and globally.
A novelty some years ago, virtual system prototyping has become a mainstay in many design flows. For instance, VaST Systems Technology will add the Virtual Processor Model Transformer (VPM-T) to its suite of virtual system prototyping software. VPM-T allows VaST users to modify the instruction set of a VaST seed virtual processor model, a capability that had only been possible throughVaST itself. The VaST seed model consists of the instruction set, micro-architecture, pipelining, and other behavior of a specific microprocessor.
With the transformer, VaST users themselves can now generate a new Virtual Processor Model in the same microprocessor family by adding, removing, or replacing instructions in the VaST seed VPM instruction set. The behavior, timing, and mnemonic aspects of the instruction can be changed independently. As a result, a VaST VPM is easily enhanced or changed so it can be made available to software and hardware developers. The VPM Transformer, slated for release in 2006 with a one-year, time-based license, will cost $100,000.
The ESL concept has attracted attention from EDA vendors of all stripes, even those whose products traditionally targeted RTL. At DAC, Sequence Design will demonstrate its ESL Power technology, with a product announcement scheduled to follow late this year. Sequence's ESL Power enables power estimations for SoCs at the SystemC level. First, it integrates with existing SystemC synthesis tools, giving algorithm designers the power estimations they need to optimize their algorithms. Then, it links with SystemC simulation environments for full-chip power estimation.
An ongoing trend in RTL design is the greater amount of analysis moving into the design phase. Atrenta, which has offered products based on its "predictive analysis" approach to rule checking for a few years now, will roll out its 1Team:Analyze tool. It diagnoses structural, coding, and consistency problems early in the RTL design phase.
The tool traces problems to their source, guides users to fixes, and can automatically fix some errors--even with issues that are typically discovered much later in the design cycle. These can include synchronization and SoC integration requirements, combinatorial loops, and inefficient resource usage. In addition, 1Team:Analyze validates that design constraints are correct and consistent throughout the design cycle, and it performs comprehensive electrical rules checking.
A brand-new company, Azuro, will debut at DAC with its PowerCentric clock implementation tool. With clock-network power sometimes sucking up as much as 80% of total on-chip switching power, PowerCentric offers a solution to reducing such dynamic power usage by the clocking network. The tool constitutes a unified clock-design closure engine that fixes faulty clock gating inserted early in the design flow.
Also targeting IC power consumption is Golden Gate Technology. At DAC, Golden Gate will show its Power Optimize Gold, which supports clock optimization using clock-aware placement as well as routing optimization with WiresFirst technology. The company also will roll out its Power Plan Gold tool, which automatically creates the power distribution system, including multiple-voltage islands for architectural power reduction.
ICs don't exist in isolation. They operate in the context of a package and physical power-delivery system. Sigrity's CoDesign Studio is a chip and package co-design tool that analyzes the performance of the combined power-delivery system. Unlike most power-integrity tools, CoDesign Studio analyzes critical package effects that can affect IC operation. It accounts for self and mutual parasitics of the chip, as well as all electromagnetic interactions within the package. Pricing starts at $30,000 for users of Sigrity's XcitePI and Speed2000 products.
The broader issue of EDA tool integration has vexed designers for decades. Silicon Navigator's Rocket Framework, based on the OpenAccess database, offers a way to tie together a broader range of tools through OpenAccess.
The Rocket Framework extends services beyond the core OpenAccess database to include a graphical user interface, scripting, schematic and layout visualization, and timing and library design-data organization. It includes many of the essential services required by front-end applications, layout, optimization, and analysis based on OpenAccess. Rocket Framework development seats are priced from $50,000/year.
CLOSING THE VERIFICATION GAP
If doubts linger among engineers about the EDA industry, many of them center on the topic of verification. The so-called "verification gap," or the inability to fully verify an ASIC or SoC design because of its size, complexity, and time constraints, is growing exponentially as gate sizes shrink.
One of the best hopes for addressing the verification gap is formal verification, which attempts to exhaustively analyze all simulation vectors to prove that a design is bug-free. Cadence will show its Incisive Formal Verifier, the latest installment in the expanding Incisive verification platform. Incisive Formal Verifier requires no testbench, enabling verification engineers to start earlier in the quest to turn up corner-case bugs missed by simulation, acceleration, and emulation.
An important aspect of Incisive Formal Verifier is its assertion-based nature. The tool supports the same set of assertions as the rest of the Incisive platform. Designers can start writing assertions along with their RTL, as well as employ the tool for formal analysis. Once IP blocks are integrated, those same assertions carry through to simulation, acceleration, and emulation. Incisive Formal Verifier is available now with prices starting at $120,000 for a one-year license.
While some vendors are jumping into the formal market, others are branching out from it. One example is Axiom Design Automation (formerly @HDL), which will use DAC to launch a more complete verification approach. Its package combines a fast simulator with advanced testbench automation, assertion-based verification, debugging, and coverage analysis. The MPSim simulator supports SystemVerilog, Verilog, OpenVera, and PSL to ensure continuity with existing verification methodologies. It's been designed to take advantage of multi-CPU computing environments, too.
For devotees of the MathWorks' Matlab-based offerings, its Simulink Verification and Validation tool enables users to produce a validated executable specification. With the tool and the executable spec to, engineers can perform continuous testing and verification throughout the development process. Simulink Verification and Validation is part of a model-based design flow that allows for formal testing of systems and algorithms during the modeling and simulation phase (Fig. 3).
The tool permits requirements-based design and test of models by giving designers the ability to link their requirements to formal requirements-management systems. Then they can navigate back and forth between the requirements and the models. Coverage reports can be generated to view untested design elements. Prices for Simulink Verification and Validation start at $1000.
Verification IP has become a popular means of checking proper functionality of interblock communications, particularly when standard protocols and buses are involved. Knowlent's Opal Electrical Verification Platforms (EVPs) help debug and verify the electrical or physical layer (PHY) of high-speed interfaces through DDRII, PCI Express, ATA I/II, and XAUI protocols.
Knowlent's EVPs work with Spice simulators to automate compliance tests that verify the PHY of standard interfaces. They test all parameters mandated by the specification, such as return loss, impedances, peak-to-peak differential amplitudes, random jitter, and deterministic jitter. Prices for an annual Opal EVP subscription start at $65,000.
Design complexity drives many verification teams to hardware-assisted methodologies in efforts to accelerate and extend coverage of their designs. Emulation and Verification Engineering (EVE) is coming to DAC with enhancements to its ZeBu verification platform. These include a transaction-level communication link to SystemVerilog simulation, support for SystemVerilog Assertions, and an automated design-clustering software tool for faster, easier setup.
ZeBu now offers tight integration with Synopsys' VCS simulator, which communicates at megahertz speeds with ZeBu at the transaction level of the Reference Verification Methodology (RVM) channel class. As a result, SystemVerilog transaction-level testbenches can be executed to stimulate and monitor designs implemented by ZeBu.
A 64-bit clustering software tool eases the complex task of mapping an ASIC or SoC design into ZeBu's arrays of Xilinx Virtex-II 8000 FPGAs (Fig. 4). The tool automates the entire mapping process, including breaking designs into multiple blocks, handling of complex clock trees, large buses, and routing of multiple signals through I/O pins. The clustering capability comes with the ZeBu compiler at no added cost. Both VCS/
RVM co-emulation and System Verilog Assertions support are added-cost options priced at $20,000 apiece.
Tharas Systems will unveil at DAC a significant expansion to its product line. Expect to see new capabilities, price-performance points, and greater ease of use for its line of hardware-assisted verification systems.
The new products, based on a scalable, multicore processor architecture, will support acceleration, virtual emulation, and traditional in-circuit emulation in a modular and portable form factor. Support for the Accellera SCE-MI application programming interface and transaction-level testbenches enhances hardware/software coverification.
RF simulation always presents particular challenges as RF designs grow in complexity. At DAC, Agilent Technologies' EEsof EDA division will show RF simulation technology with 10- to 100-fold speed increases. This makes practical the simulation of RF circuits with thousands of transistors and hundreds of thousands of parasitic elements. The technology will be incorporated into the next revisions of EEsof's ADS and RFDE platforms. ED Online 10352
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