Electronic Design

David Maliniak’s DesignCon Blog: Day 1

The 2006 edition of DesignCon kicked off Monday at the Santa Clara Convention Center with something less than a bang. It’s indicative of where technical conferences find themselves in these times when a full day of technical forums and panels can find itself so lightly attended. Weather was certainly not a detriment here in the Valley. Perhaps things will pick up when exhibits open on Tuesday.

For this correspondent, Monday brought a light schedule of meetings, leaving some time to survey the conference’s offerings. The technical program at DesignCon is a compact one, but it spans a broad swath of topics of interest to the electronic design engineer. Papers are presented in tracks such as application-specific design, chip-level functional design, functional verification, chip and package co-design, and others. There’s a good amount of concentration on high-speed design, with tracks on the design of multi-gigabit backplanes as well as high-speed timing, jitter, and noise.

Given my personal predilection toward things EDA, there are management forum panels of particular interest. I’m looking forward to a Tuesday panel that will ask the penetrating question, “Why is EDA stagnating, or is it?” Indeed, some industry observers of late have wondered what will lift EDA out of its persistent doldrums. The notion is spoken to further by another panel, this one on Wednesday, that will explore the growing cost of EDA tools and when it makes sense for tool consumers to build their own tools as opposed to buying them on the open market. The prospect of EDA reverting to its nascent stage, when the electronic industry’s early integrated device manufacturers largely relied on their own homebrewed design tools, surely elicits some dread from EDA vendors.

Other sessions on the EDA front are of a more positive nature, at least on their faces. A DFM panel on Tuesday will look at what needs to be done to close the gaps threatening yield at 65 nm and beyond. And if you still haven’t drunk the electronic system-level (ESL) Kool-aid, a Wednesday panel will explore the business implications of ESL.

As the week progresses, I’ll continue to keep you updated on the highlights from DesignCon. Stay tuned.

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