EE Product News

DDR DIMM Interface Built With Three ICs

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With just three ICs, designers reportedly can build a complete interface for 184-pin, 2.5V PC200/PC266, 72-bit-wide registered double data rate (DDR) SDRAM memory modules. The three members of the DDR DIMM interface chipset include: the FMS7857 phase locked loop (PLL) clock driver; the SSTV16857 registered buffer; and the FM34W02 serial presence detect EEPROM.
Operating over a 95 to 170 MHz frequency range, the 48-pin TSSOP PLL clock driver is a zero-delay clock buffer used to synchronize signals to each memory chip. The 48-pin TSSOP registered buffer is a 14-bit register used for address and control buffering. And the 8-pin TSSOP 2-Kbit, 2-wire bus interface EEPROM allows the CPU to determine the module's capacity and electrical characteristics of its memory devices. The FMS7857 costs $4 each/1,000; SSTV16857, $4.25; and FM34W02, $0.80.

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